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TURBO-DECO-O4-N1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Lattice Semiconductor Turbo Decoder User’s Guide
10
Signal Descriptions
Table 2 shows the signal descriptions for the input and output ports of the Turbo Decoder IP core.
Table 2. Turbo Decoder Signal Definitions
Port Name I/O Type Width Signal Description
clk Input 1 System Clock
rstn Input 1 Active Low Asynchronous Reset
sr Input 1 Synchronous Reset
din Input 3-6 Data Input (soft encoded data from demodulator)
dout Output 1 Data Output
iterations Input 4 Input bus to set the number of decoding iterations. The valid values are from
1 to 15.
blocksiz-
eset(ipcfgset)
Input 1 Interleaver initialization. blocksize on input pins can be changed and
accepted when this signal is asserted.
inpvalid Input 1 Enables the decoder to read the data at din when asserted.
rfi Output 1 Active High signal. Indicates that decoder is available to accept data. This
signal is de-asserted one data symbol before buffer is full.
blocksize Input 13-15 Block size up to 20730 bits can be set depending on the configuration
selected. Block size ranges:
3GPP: 40-5114
3GPP2: 378-20730
CCSDS: 1784, 3568, 7136, 8920
rfno Input 1 Asserted to indicate successful reading of encoded data from dout.
rfo Output 1 When asserted encoded data is ready and available at dout.
rate Input 1 or 2 Determines the rate of the Turbo Decoder
For 3GPP, size 1 bit, 0-rate 1/3 and 1- rate 1/2
For 3GPP2, size 2 bits, 0-rate 1/2, 1- rate 1/3, 2- rate 1/4 and 3- rate 1/5
For CCSDS, size 2 bits, 0-rate 1/2, 1- rate 1/3, 2- rate 1/4 and 3- rate 1/6
Lattice Semiconductor Turbo Decoder User’s Guide
11
Additional Signals for External Memory
When external memory is used with this core additional signals are provided to form the interface to the external
memory. These are detailed below.
3GPP
In the case where external memory is selected, the I/O pins in Table 3 will be added to the block for exchanging
data with the memory in the case of 3GPP. It is assumed that data and parity are stored in different memory buff-
ers. Non-interleaved and interleaved parity are stored in different buffers.
Table 3. Additional I/Os Due to External Memory for 3GPP
In the case where double buffering is selected along with the external memory the I/O pins in Table 4 will also be
added to the core for exchanging data with the second buffer in the case of 3GPP.
Table 4. Additional I/Os Due to Double Buffering for 3GPP
Port Name I/O Type Width Signal Description
g1_dat_buf1
Input 3-6
Information data port 1
g2_dat_buf1
Input 3-6
Information data port 2
g1_par_odd1
Input 3-6
Parity 1 (systematic) data port 1
g2_par_odd1
Input 3-6
Parity 1 (systematic) data port 2
g1_par_even1
Input 3-6
Parity 2 (interleaved) data port 1
g2_par_even1
Input 3-6
Parity 2 (interleaved) data port 2
data_to_mem
Output 3-6
Information/parity data to memory
data_waddr
Output 3-6
Information/parity Write address
wren_dat_buf1
Output 1
Write enable for Information data
wren_par1_buf1
Output 1
Write enable for parity 1 (systematic)
wren_par2_buf1
Output 1
Write enable for parity 2 (interleaved)
g1_rden
Output 1
Information/parity read enable port 1
g2_rden
Output 1
Information/parity read enable port 2
g1_dat_raddr
Output 11-15
Information read address port 1
g2_dat_raddr
Output 11-15
Information read address port 2
g1_par_raddr
Output 11-15
Parity read address port 1
g2_par_raddr
Output 11-15
Parity read address port 2
Port Name I/O Type Width Signal Description
g1_dat_buf2 Input
3-6
Information data port 1
g2_dat_buf2 Input
3-6
Information data port 2
g1_par_odd2 Input
3-6
Parity 1 (systematic) data port 1
g2_par_odd2 Input
3-6
Parity 1 (systematic) data port 2
g1_par_even2 Input
3-6
Parity 2 (interleaved) data port 1
g2_par_even2 Input
3-6
Parity 2 (interleaved) data port 2
wren_dat_buf2 Output 1 Write enable for Information data
wren_par1_buf2 Output 1 Write enable for parity 1 (systematic)
wren_par2_buf2 Output 1 Write enable for parity 2 (interleaved)
Lattice Semiconductor Turbo Decoder User’s Guide
12
CCSDS
For CCSDS decoder type, in the case that an external memory is selected; the following additional pins are
required. It is assumed that data and parity are stored in different memory buffers. Non-interleaved and interleaved
parity are stored in different buffers.
Table 5. Additional I/Os Due to External Memory for CCSDS
In the case where double buffer is selected along with the external memory the I/O pins in Table 6 will also be
added to the core for exchanging data with the second buffer in the case of CCSDS.
Table 6. Additional I/Os Due to Double Buffering for CCSDS
Port Name I/O Type Width Signal Description
g1_par2_odd1 Input 3-6 Parity 3 (systematic) data port 1
g2_par2_odd1 Input 3-6 Parity 3 (systematic) data port 2
g1_par3_odd1 Input 3-6 Parity 4 (systematic) data port 1
g2_par3_odd1 Input 3-6 Parity 4 (systematic) data port 2
g1_par3_even1 Input 3-6 Parity 5 (interleaved) data port 1
g2_par3_even1 Input 3-6 Parity 5 (interleaved) data port 2
wren_par3_buf1 Output 1 Write enable for parity 3 (systematic)
wren_par4_buf1 Output 1 Write enable for parity 4 (systematic)
wren_par5_buf1 Output 1 Write enable for parity 5 (interleaved)
Note: These ports are in addition to the ports listed for 3GPP in Table 3.
Port Name I/O Type Width Signal Description
g1_par2_odd2 Input 3-6 Parity 3 (systematic) data port 1
g2_par2_odd2 Input 3-6 Parity 3 (systematic) data port 2
g1_par3_odd2 Input 3-6 Parity 4 (systematic) data port 1
g2_par3_odd2 Input 3-6 Parity 4 (systematic) data port 2
g1_par3_even2 Input 3-6 Parity 5 (interleaved) data port 1
g2_par3_even2 Input 3-6 Parity 5 (interleaved) data port 2
wren_par3_buf2 Output 1 Write enable for parity 3 (systematic)
wren_par4_buf2 Output 1 Write enable for parity 4 (systematic)
wren_par5_buf2 Output 1 Write enable for parity 5 (interleaved)
Note: These ports are in addition to the ports listed for 3GPP in Table 4.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

TURBO-DECO-O4-N1

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Development Software Turbo Decoder
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