Lattice Semiconductor Turbo Decoder User’s Guide
13
3GPP2
For the 3GPP2 decoder type, in the case that an external memory is selected; the following additional pins are
required. It is assumed that data and parity are stored in different memory buffers. Non-interleaved and interleaved
parity are stored in different buffers.
Table 7. Additional I/Os Due to External Memory for 3GPP2
In the case where a double buffer is selected along with the external memory, the I/O pins in Table 8 will also be
added to the core for exchanging data with the second buffer in the case of 3GPP2.
Table 8. Additional I/Os Due to Double Buffering for 3GPP2
IPexpress™ User-Configurable Core
The Turbo Decoder core is an IPexpress User-Configurable IP core, which allows designers to configure the IP and
generate netlists as well as simulation files for use in designs. The IPexpress flow also supports a hardware evalu-
ation capability, making it possible to create versions of the IP core that operate in hardware for a limited period of
time without requiring the purchase of an IP license.
To download a full evaluation version of this IP core, please go to the Lattice IP Server tab in the ispLEVER
®
IPex-
press GUI window. All ispLeverCORE™ IP cores available for download are visible on this tab.
References
The Lattice Turbo Decoder IP core is compliant with two standards: 3GPP and CCSDS. More information about
each standard can be referenced at the following locations.
• The 3rd Generation Partnership Project (www.3gpp.org) provides specifications to 3GPP TS 25.212 v4.2.0
(2001-09) standards.
• The Consultative Committee for Space Data Systems (www.ccsds.org) provides specifications to CCSDS 101.0-
B-5 standards.
Port Name I/O Type Width Signal Description
g1_par2_odd1 Input 3-6 Parity 3 (systematic) data port 1
g2_par2_odd1 Input 3-6 Parity 3 (systematic) data port 2
g1_par2_even1 Input 3-6 Parity 4 (interleaved) data port 1
g2_par2_even1 Input 3-6 Parity 4 (interleaved) data port 2
wren_par3_buf1 Output 1 Write enable for parity 3 (systematic)
wren_par4_buf1 Output 1 Write enable for parity 4 (interleaved)
Note: These ports are in addition to the ports listed for 3GPP in Table 3.
Port Name I/O Type Width Signal Description
g1_par2_odd2 Input 3-6 Parity 3 (systematic) data port 1
g2_par2_odd2 Input 3-6 Parity 3 (systematic) data port 2
g1_par2_even2 Input 3-6 Parity 4 (interleaved) data port 1
g2_par2_even2 Input 3-6 Parity 4 (interleaved) data port 2
wren_par3_buf2 Output 1 Write enable for parity 3 (systematic)
wren_par4_buf2 Output 1 Write enable for parity 4 (interleaved)
Note: These ports are in addition to the ports listed for 3GPP in Table 4.
