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MAX6795TPLD1+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
MAX6791–MAX6796
High-Voltage, Micropower, Single/Dual Linear
Regulators with Supervisory Functions
16 ______________________________________________________________________________________
Watchdog Timer
The MAX6791–MAX6796 include a watchdog timer
that asserts RESET if the watchdog input (WDI) does
not toggle high to low or low to high within the watch-
dog timeout period t
WD
(280ms min or externally
adjustable). RESET remains low for the fixed or user-
adjustable reset timeout period, t
RP
. If the watchdog is
not updated for lengthy periods of time, the reset out-
put appears as a pulse train, asserted for t
RP
,
deasserted for t
WD
, until WDI is toggled again. Once
RESET asserts, it stays low for the entire reset timeout
period ignoring any WDI transitions that may occur. To
prevent the watchdog from asserting RESET, toggle
WDI with a valid rising or falling edge before t
WD
from
the last edge. The watchdog counter clears when WDI
toggles prior to t
WD
from the last edge or when RESET
asserts. The watchdog resumes counting after RESET
deasserts.
The MAX6791/MAX6792 have a windowed watchdog
timer that asserts RESET for the adjusted reset timeout
period when the watchdog recognizes a fast watchdog
fault (t
WDI
< t
WD1
), or a slow watchdog fault (t
WDI
>
t
WD2
). The reset timeout period is adjusted indepen-
dently of the watchdog timeout period.
Enable and Hold Inputs
The MAX6791–MAX6796 support two logic inputs,
ENABLE1/ENABLE and HOLD, making these devices
suitable for automotive applications. For example, when
the ignition key signal drives ENABLE1/ENABLE high,
the regulator turns on and remains on even if
ENABLE1/ENABLE goes low, as long as HOLD is forced
low and stays low after initial regulator power-up. In this
state, releasing HOLD turns the regulator output
(OUT/OUT1) off. This feature makes it possible to imple-
ment a self-holding circuit without external components.
Forcing ENABLE1/ENABLE low and HOLD high or
unconnected places the MAX6791–MAX6796 into shut-
down mode in which the MAX6791–MAX6796 draw less
than 27µA of supply current.
Table 3 shows the state of the regulator output with
respect to the voltage level at ENABLE1/ENABLE and
HOLD. Connect HOLD to OUT1/OUT or leave it uncon-
nected to allow the ENABLE1/ENABLE input to act as a
standard ON/OFF switch for the regulator output
(OUT/OUT1).
Power-Fail Comparator
PFI is the noninverting input to a comparator. If PFI is
less than V
PFI
(1.231V), PFO goes low. Common uses
for the power-fail comparator include monitoring the
preregulated input of the power supply (such as a bat-
tery) or providing an early power-fail warning so soft-
ware can conduct an orderly system shutdown. Set the
power-fail threshold with a resistive-divider, as shown in
Figure 5. The typical comparator delay is 35µs from PFI
to PFO. Connect PFI to GND or IN if unused.
Reverse-Battery Protection Circuitry
The MAX6791–MAX6796 include an overvoltage pro-
tection circuit that is capable of driving a p-channel
MOSFET to protect against reverse-battery conditions.
This MOSFET eliminates the need for external diodes,
thus minimizing the input voltage drop. See the
Typical
Application Circuit
. The low p-channel MOSFET on-
resistance of 30mΩ or less yields a forward-voltage
drop of only a few millivolts versus hundreds of milli-
volts for a diode, thus improving efficiency in battery-
operated devices. Connecting a positive battery
voltage to the drain of Q1 (see the
Typical Application
Circuit
) forward biases its body diode. When the source
voltage exceeds Q1’s threshold voltage, Q1 turns on.
Once the FET is on, the battery is fully connected to the
system and can deliver power to the device and the
load. An incorrectly inserted battery reverse-biases the
FET’s body diode. The gate remains at the ground
potential. The FET remains off and disconnects the
reversed battery from the system. The internal zener
diode and resistor combination at GATEP prevent dam-
age to the p-channel MOSFET during an overvoltage
condition. See the
Functional Diagrams
.
Thermal Protection
When the junction temperature exceeds T
J
= +165°C,
the internal protection circuit turns off the internal pass
transistor and allows the IC to cool. The thermal sensor
turns the pass transistor on again after the junction tem-
perature drops to +145°C, resulting in a cycled output
during continuous thermal-overload conditions.
Thermal protection protects the MAX6791–MAX6796 in
the event of fault conditions. For continuous operation,
do not exceed the absolute maximum junction temper-
ature rating of +150°C.
Proper Soldering of Package Heatsink
The MAX6791–MAX6796 package features an exposed
thermal pad on its underside that should be used as a
heatsink. This pad lowers the package’s thermal resis-
tance by providing a direct heat-conduction path from
the die to the PC board. Connect the exposed pad and
GND to the system ground using a large pad or ground
plane, or multiple vias to the ground plane layer.
MAX6791–MAX6796
High-Voltage, Micropower, Single/Dual Linear
Regulators with Supervisory Functions
______________________________________________________________________________________ 17
Applications Information
Output Voltage Selection
The MAX6791–MAX6796 feature dual-mode operation:
these devices operate in either a preset voltage mode
or an adjustable mode. In preset voltage mode, internal
trimmed feedback resistors set the internal linear regula-
tor to +1.8V, +2.5V, +3.3V, or +5V (see the
Selector
Guide
). Select preset voltage mode by connecting SET1
(MAX6791–MAX6794)/SET(MAX6795/MAX6796) to
GND. In adjustable mode, select an output voltage
between +1.8V and +11V using two external resistors
connected as a voltage-divider to SET1/SET (see Figure
1). Set the output voltage using the following equation:
where V
SET
= 1.2315V and R1, R2 ≤ 200kΩ.
Available Output-Current Calculation
The MAX6791–MAX6794 provide up to 150mA per out-
put, and the MAX6795/MAX6796 provide up to 300mA
of load current. Since the input voltage can be as high
as +72V, package power dissipation limits the amount
of output current available for a given input/output volt-
age and ambient temperature. Figure 2 shows the max-
imum power-dissipation curve for the MAX6791–
MAX6796. The graph assumes that the exposed metal
pad of the device package is soldered to a solid 1in
2
section of PC board copper. Use Figure 2 to determine
the allowable package dissipation for a given ambient
temperature. Alternately, use the following formula to
calculate the allowable package dissipation:
PD
MAX
= Maximum Power Dissipation
PD
MAX
= 2.666W, for T
A
≤ +70°C
PD
MAX
= [2.666W - 0.0333W x (T
A
- 70°C)], for +70°C
< T
A
≤ +125°C
where 0.0333W is the MAX6791–MAX6796 package
thermal derating in W/°C and T
A
is the ambient temper-
ature in °C.
After determining the allowable package dissipation,
calculate the maximum output current using the follow-
ing formula:
PD = Power Dissipation
PD < PD
MAX
where PD = [(IN - OUT1) x I
OUT1
] + [(IN -
OUT2) x I
OUT2
], for MAX6791–MAX6794.
Also, I
OUT1
should be ≤ 150mA and I
OUT2
should be
≤ 150mA in any case.
PD < PD
MAX
where PD = [(IN - OUT) x I
OUT
], for
MAX6795/MAX6796.
Also, I
OUT
should be ≤ 300mA in any case.
Selecting Reset Timeout Period
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period by connecting a capacitor between CSRT and
GND. Use the following formula to set the reset timeout
period:
where t
RP
is in seconds and C
CSRT
is in Farads.
Connect CSRT to OUT1 (MAX6791–MAX6794) or to
OUT (MAX6795/MAX6796) to select an internally fixed
timeout period. Connect CSRT to GND to force RESET
low. C
CSRT
must be a low-leakage (< 10nA) type
capacitor. Ceramic capacitors are recommended; do
not use capacitors lower than 100pF to avoid the influ-
ence of parasitic capacitances.
tC
V
A
RP CSRT
. =×
⎛
⎝
⎜
⎞
⎠
⎟
1 218 10
6
VV
R
R
OUT SET
=+
⎛
⎝
⎜
⎞
⎠
⎟
1
1
2
MAX6791–MAX6796
V
IN
R1
R2
OUT1/OUT
SET1/SET
IN
GND
Figure 1. Setting the Output Voltage Using a Resistive-Divider
I
OUT
vs. (V
IN
- V
OUT
)
(V
IN
- V
OUT
) (V)
I
OUT
(mA)
70 75605040302010
50
100
150
200
250
300
350
0
0
+70°C
+85°C
+125°C
V
OUT
= 1.8V
SAFE OPERATION REGION FOR
EACH TEMPERATURE POINT IS
UNDER THE CURVE
Figure 2. Maximum Power Dissipation for MAX6791–MAX6796
MAX6791–MAX6796
High-Voltage, Micropower, Single/Dual Linear
Regulators with Supervisory Functions
18 ______________________________________________________________________________________
Selecting Watchdog Timeout Period
The watchdog timeout period is adjustable to accommo-
date a variety of µP applications. With this feature, the
watchdog timeout can be optimized for software execu-
tion. The programmer can determine how often the
watchdog timer should be serviced. Adjust the watch-
dog timeout period (t
WD
) by connecting a capacitor
between CSWT and GND. For normal-mode operation,
calculate the watchdog timeout capacitor as follows:
where t
WD
is in seconds and C
CSWT
is in Farads.
To select the internally fixed watchdog timeout period
for the MAX6791–MAX6794, connect CSWT to OUT1.
To select the internally fixed watchdog timeout period
for the MAX6795/MAX6796, connect CSWT to OUT.
C
CSWT
must be a low-leakage (< 10nA) type capacitor.
Ceramic capacitors are recommended; do not use
capacitors lower than 100pF to avoid the influence of
parasitic capacitances.
The MAX6791/MAX6792 have a windowed watchdog
timer that asserts RESET for t
RP
when the watchdog
recognizes a fast watchdog fault (time between transi-
tions < t
WD1
), or a slow watchdog fault (time between
transitions > t
WD2
). The reset timeout period is adjust-
ed independently of the watchdog timeout period. The
slow watchdog period, t
WD2
, is calculated as follows:
where t
WD2
is in seconds and C
CSWT
is in Farads.
The fast watchdog period, t
WD1
, is selectable as a ratio
from the slow watchdog fault period (t
WD2
). Select the
fast watchdog period by connecting WDS0 and WDS1 to
OUT/OUT1 or GND according to Table 4, which illus-
trates the settings for the 8, 16, and 64 window ratios
(t
WD2
/t
WD1
). For example, if C
CSWT
is 2000pF, and
WDS0 and WDS1 are low, then t
WD2
is 318ms (typ) and
t
WD1
is 40ms (typ). RESET asserts if the watchdog input
has two edges too close to each other (faster than t
WD1
);
or has edges that are too far apart (slower than t
WD2
).
All WDI inputs are ignored while RESET is asserted. The
watchdog timer begins to count after RESET is
deasserted. If the time difference between two transi-
tions on WDI is shorter than t
WD1
or longer than t
WD2
,
RESET is forced to assert low for the reset timeout peri-
od. If the time difference between two transitions on WDI
is between t
WD1
(min) and t
WD1
(max) or t
WD2
(min)
and t
WD2
(max), RESET is not guaranteed to assert or
deassert; see Figure 3. To guarantee that the window
watchdog does not assert RESET, strobe WDI between
t
WD1
(max) and t
WD2
(min). The watchdog timer is
cleared when RESET is asserted. Disable the watchdog
timer by connecting WDS0 high and WDS1 low.
There are several options available to disable the
watchdog timer (for system development or test pur-
poses or when the µP is in a low-power sleep mode).
One way to disable the watchdog timer is to drive
WD-DIS low for the MAX6793–MAX6796 and drive
WDS0 high and WDS1 low for the MAX6791/MAX6792.
This prevents the capacitor from ramping up. Finally,
reducing the OUT/OUT1 regulator current below the
specified regulator current watchdog-disable threshold
(3mA min) also disables the watchdog timer. The
tC
V
A
WD CSWT2
6
155 10 =×
⎛
⎝
⎜
⎞
⎠
⎟
tC
V
A
WD CSWT2
6
155 10 =×
⎛
⎝
⎜
⎞
⎠
⎟
t
WD1
t
WD2
t
WD0
MIN
GUARANTEED
TO ASSERT
UNDETERMINED UNDETERMINED
GUARANTEED
TO NOT ASSERT
GUARANTEED
TO ASSERT
FAST
FAULT
NORMAL
OPERATION
SLOW
FAULT
RESET:
WDI INPUT:
MAX MIN MAX
Figure 3. Windowed Watchdog Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

MAX6795TPLD1+

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Manufacturer:
Maxim Integrated
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Linear Voltage Regulators Single uPower Linear
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