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5T905PGGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
5T905 DATA SHEET
10 REVISION A 11/3/15
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to fl oat or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifi es the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only.
The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new
state.
4. VCM specifi es the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is constrained within +600mV
and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specifi ed in the JEDEC 1.8V LVTTL interface
specifi cation, VREF must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced.
10. This value is the worst case minimum VIH over the specifi cation range of the 1.8V power supply. The 1.8V LVTTL specifi cation is VIH = 0.65 • VDD where VDD is 1.8V ± 0.15V. However,
the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specifi cation, the translator was designed to accept the calculated worst case
value ( VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specifi cation range of the 1.8V power supply. The 1.8V LVTTL specifi cation is VIL = 0.35 • VDD where VDD is 1.8V ± 0.15V. However,
the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specifi cation, the translator was designed to accept the calculated worst case
value ( VIH = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V
LVTTL
(1)
Symbol Parameter Test Conditions Min. Typ.
(8)
Max Unit
Input Characteristics
I
IH Input HIGH Current
(12)
VDD = 2.6V VI = VDDQ/GND — — ±5 μA
I
IL Input LOW Current
(12)
VDD = 2.6V VI = GND/VDDQ — — ±5
V
IK Clamp Diode Voltage VDD = 2.4V, IIN = -18mA — - 0.7 - 1.2 V
V
IN DC Input Voltage - 0.3 VDDQ + 0.3 V
Single-Ended Inputs
(2)
VIH DC Input HIGH 1.073
(10)
— V
V
IL DC Input LOW — 0.683
(11)
V
Differential Inputs
V
DIF DC Differential Voltage
(3,9)
0.2 — V
V
CM DC Common Mode Input Voltage
(4,9)
825 900 975 mV
V
IH DC Input HIGH
(5,6,9)
VREF + 100 — mV
V
IL DC Input LOW
(5,7,9)
— VREF - 100 mV
V
REF Single-Ended Reference Voltage
(5,9)
— 900 — mV
Output Characteristics
V
OH Output HIGH Voltage IOH = -6mA VDDQ - 0.4 — V
I
OH = -100μA VDDQ - 0.1 — V
V
OL Output LOW Voltage IOL = 6mA — 0.4 V
I
OL = 100μA — 0.1 V
REVISION A 11/3/15
5T905 DATA SHEET
11 2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS
(1)
Symbol Parameter Test Conditions
(2)
Typ. Max Unit
I
DDQ Quiescent VDD Power Supply Current VDDQ = Max., Reference Clock = LOW
(3)
20 30 mA
Outputs enabled, All outputs unloaded
I
DDQQ Quiescent VDDQ Power Supply Current VDDQ = Max., Reference Clock = LOW
(3)
0.1 0.3 mA
Outputs enabled, All outputs unloaded
I
DDD Dynamic VDD Power Supply VDD = Max., VDDQ = Max., CL = 0pF 20 30 μA/MHz
Current per Output
I
DDDQ Dynamic VDDQ Power Supply VDD = Max., VDDQ = Max., CL = 0pF 20 30 μA/MHz
Current per Output
I
TOT Total Power VDD Supply Current VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF 20 30 mA
V
DDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF 30 40
I
TOTQ Total Power VDDQ Supply Current VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF 20 40 mA
V
DDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF 45 80
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol Parameter Value Units
V
IH Input HIGH Voltage
(1)
VDDI V
V
IL Input LOW Voltage 0 V
V
THI Input Timing Measurement Reference Level
(2)
VDDI/2 mV
t
R, tF Input Signal Edge Rate
(3)
2 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specifi ed to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol Parameter Value Units
V
DIF Input Signal Swing
(1)
VDDI V
V
X Differential Input Signal Crossing Point
(2)
VDDI/2 mV
V
THI Input Timing Measurement Reference Level
(3)
Crossing Point V
t
R, tF Input Signal Edge Rate
(4)
1.8 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specifi ed to allow consistent, repeatable results
in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specifi cation under actual use conditions.
2. A nominal 900mV crossing point level is specifi ed to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX spec-
ifi cation under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™
5T905 DATA SHEET
12 REVISION A 11/3/15
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
(6)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
t
SK(O) Same Device Output Pin-to-Pin Skew
(1)
Single-Ended and Differential Modes — — 60 ps
Single-Ended in Differential Mode (DSE) — 60 —
t
SK(P)
(2)
Pulse Skew
(3)
Single-Ended and Differential Modes — — 300 ps
Single-Ended in Differential Mode (DSE) — 300 —
d
T
(4)
Duty Cycle 40 — 60 %
t
SK(PP) Part-to-Part Skew
(5)
Single-Ended and Differential Modes — — 300 ps
Single-Ended in Differential Mode (DSE) — 300 —
Propagation Delay
t
PLH Propagation Delay A to Qn — — 2.5 ns
tPHL
tR Output Rise Time (20% to 80%) 2.5V / 1.8V LVTTL Outputs 350 — 1050 ps
HSTL / eHSTL Outputs 350 — 1350
t
F Output Fall Time (20% to 80%) 2.5V / 1.8V LVTTL Outputs 350 — 1050 ps
HSTL / eHSTL Outputs 350 — 1350
f
O Frequency Range (HSTL/eHSTL outputs)
— — 250 MHz
Frequency Range (2.5V/1.8V LVTTL outputs)
— — 200
Output Gate Enable/Disable Delay
t
PGE Output Gate Enable to Qn
— — 3.5 ns
t
PGD Output Gate Enable to Qn Driven to GL Designated Level
— — 3 ns
NOTES:
1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device.
2. For only 1.8V/2.5V LVTTL and eHSTL outputs.
3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device.
4. For only HSTL outputs.
5. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels
and temperature.
6. Guaranteed by design.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

5T905PGGI8

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Clock Buffer 2.5V 1:5 TeraBuffer Clock Driver w/Signa
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