7
FN2974.4
September 9, 2015
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
I82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
M82C84A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Thermal Resistance. . . . . . . . . . . . . . . . .
JA
(
o
C/W)
JC
(
o
C/W)
CERDIP Package. . . . . . . . . . . . . . . . . 80 20
CLCC Package . . . . . . . . . . . . . . . . . . 95 28
PDIP Package* . . . . . . . . . . . . . . . . . . 85 N/A
PLCC Package. . . . . . . . . . . . . . . . . . . 85 N/A
Storage Temperature Range . . . . . . . . . . . . . . . . . -65
o
C to +150
o
C
Max Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+175
o
C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300
o
C
(PLCC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications V
CC
= +5.0V10%,
T
A
= 0
o
C to +70
o
C (C82C84A),
T
A
= -40
o
C to +85
o
C (I82C84A),
T
A
= -55
o
C to +125
o
C (M82C84A)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
V
IH
Logical One Input Voltage 2.0
2.2
-V
V
C82C84A, I82C84
M82C84A, Notes 1, 2
V
IL
Logical Zero Input Voltage - 0.8 V Notes 1, 2, 3
V
IHR
Reset Input High Voltage V
CC
-0.8 - V
V
ILR
Reset Input Low Voltage - 0.5 V
VT+ - VT- Reset Input Hysteresis 0.2 V
CC
--
V
OH
Logical One Output Current V
CC
-0.4 - V I
OH
= -4.0mA for CLK Output
I
OH
= -2.5mA for All Others
V
OL
Logical Zero Output Voltage - 0.4 V I
OL
= +4.0mA for CLK Output
I
OL
= +2.5mA for All Others
II Input Leakage Current -1.0 1.0 AV
IN
= V
CC
or GND except ASYNC,
X1: (Note 4)
I
CCOP
Operating Power Supply Current - 40 mA Crystal Frequency = 25MHz
Outputs Open, Note 5
NOTES:
1. F/C
is a strap option and should be held either 0.8V or 2.2V. Does not apply to X1 or X2 pins.
2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is
guaranteed.
3. CSYNC
pin is tested with V
IL
0.8V.
4. ASYNC
pin includes an internal 17.5k nominal pull-up resistor. For ASYNC input at GND, ASYNC input leakage current = 300A
nominal, X1 - crystal feedback input.
5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz.
Capacitance T
A
= +25
o
C
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
C
IN
Input Capacitance 10 pF FREQ = 1MHz, all measurements are
referenced to device GND
C
OUT
Output Capacitance 15 pF
82C84A82C84A
8
FN2974.4
September 9, 2015
AC Electrical Specifications V
CC
= +5V 10%,
T
A
= 0
o
C to +70
o
C (C82C84A),
T
A
= -40
o
C to +85
o
C (I82C84A),
T
A
= -55
o
C to +125
o
C (M82C84A)
SYMBOL PARAMETER
LIMITS
UNITS
(NOTE 1)
TEST
CONDITIONS MIN MAX
TIMING REQUIREMENTS
(1) TEHEL External Frequency HIGH Time 13 - ns 90%-90% V
IN
(2) TELEH External Frequency LOW Time 13 - ns 10%-10% V
IN
(3) TELEL EFI Period 36 - ns
XTAL Frequency 2.4 25 MHz Note 2
(4) TR2VCL RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = HIGH
(5) TR1VCH RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = LOW
(6) TR1VCL RDY1, RDY2 Inactive Setup to CLK 35 - ns
(7) TCLR1X RDY1, RDY2 Hold to CLK 0 - ns
(8) TAYVCL ASYNC
Setup to CLK 50 - ns
(9) TCLAYX ASYNC
Hold to CLK 0 - ns
(10) TA1VR1V AEN1
, AEN2 Setup to RDY1, RDY2 15 - ns
(11) TCLA1X AEN1
, AEN2 Hold to CLK 0 - ns
(12) TYHEH CSYNC Setup to EFI 20 - ns
(13) TEHYL CSYNC Hold to EFI 20 - ns
(14) TYHYL CSYNC Width 2
TELEL - ns
(15) TI1HCL RES
Setup to CLK 65 - ns Note 3
(16) TCLI1H RES
Hold to CLK 20 - ns Note 3
TIMING RESPONSES
(17) TCLCL CLK Cycle Period 125 - ns Note 6
(18) TCHCL CLK HIGH Time (1/3 TCLCL) +2.0 - ns Note 6
(19) TCLCH CLK LOW Time (2/3 TCLCL) -15.0 - ns Note 6
(20)
(21)
TCH1CH2
TCL2CL1
CLK Rise or Fall Time - 10 ns 1.0V to 3.0V
(22) TPHPL PCLK HIGH Time TCLCL-20 - ns Note 6
(23) TPLPH PCLK LOW Time TCLCL-20 - ns Note 6
(24) TRYLCL Ready Inactive to CLK (See Note 4) -8 - ns Note 4
(25) TRYHCH Ready Active to CLK (See Note 3) (2/3 TCLCL) -15.0 - ns Note 5
(26) TCLIL CLK to Reset Delay - 40 ns
(27) TCLPH CLK to PCLK HIGH Delay - 22 ns
(28) TCLPL CLK to PCLK LOW Delay - 22 ns
(29) TOLCH OSC to CLK HIGH Delay -5 22 ns
(30) TOLCL OSC to CLK LOW Delay 2 35 ns
NOTES:
1. Tested as follows: f = 2.4MHz, V
IH
= 2.6V, V
IL
= 0.4V, C
L
= 50pF, V
OH
1.5V, V
OL
1.5V, unless otherwise specified. RES and F/C must switch
between 0.4V and V
CC
-0.4V. Input rise and fall times driven at 1ns/V. V
IL
V
IL
(max) - 0.4V for CSYNC pin. V
CC
= 4.5V and 5.5V.
2. Tested using EFI or X1 input pin.
3. Setup and hold necessary only to guarantee recognition at next clock.
4. Applies only to T2 states.
5. Applies only to T3 TW states.
6. Tested with EFI input frequency = 4.2MHz.
82C84A82C84A
9
FN2974.4
September 9, 2015
Timing Waveforms
NOTE: All timing measurements are made at 1.5V, unless otherwise noted.
FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS
FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
FIGURE 4. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)
tEHYL
(13)
NAME
EFI
OSC
CLK
PCLK
CSYNC
RES
RESET
I/O
I
O
O
O
O
I
I
tYHYL
(14)
(12)
tYHEH
(20)
tCH1CH2
(29)
tOLCH
tELEL
(3)
(30)
tOLCL
(21)
tCL2CL1
(27)
tCLPH
(23)
tPLPH
tCLI1H
(16)
tCLCH
(19)
(17) tCLCL
tCLIL
(26)
(28)
tCLPL
(18)
tCHCL
(1)
tEHEL
(2)
tELEH
tPHPL
(22)
tI1HCL
(15)
tCLR1X
tR1VCH
(5)
tA1VR1V
(7)
(10)
tAYVCL
(8)
tCLAYX
(9)
(25)
tRYHCH
(11)
(24) tRYLCL
tCLA1X
(7)tCLR1X
tR1VCL
(6)
CLK
RDY1, 2
AEN1
, 2
ASYNC
READY
CLK
RDY 1, 2
READY
ASYNC
AEN1, 2
(25)
tRYHCH
(24)
tRYLCL
tCLR1X
(8)
(4)
(7)
(9)
(11)
(7)
(6)
(10)
tR1VCL
tCLR1X
tCLA1X
tR1VCL
tAYVCL
tCLAYX
tA1VRIV
82C84A82C84A

CS82C84AZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Clock Generators & Support Products PERIPH CLK GENERATOR 5V 25MHZ 20PLCC COM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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