EVB-EN6360QI

Enpirion
®
Power Evaluation Board User Guide
EN6360QI PowerSoC
STEP 5: Connect Power Supply to the input power connectors, VIN (J7) and
GND (J11) as indicated in Figure 4 and set the power supply to the desired
voltage (≤6.6V.)
CAUTION: Be mindful of the polarity. Even though the evaluation board
comes with reverse polarity protection diodes, it is rarely a good idea to
reverse the input polarity.
STEP 6: Connect the load to the output connectors VOUT (J6) and GND (J10),
as indicated in Figure 4.
STEP 7: Power up the board and move the ENA jumper to the enabled position.
The EN6360QI is now powered up and generating the desired output. You are
free to make Efficiency, Ripple, Line/Load Regulation, Load transient, Power OK,
over current limit and temperature related measurements.
STEP 7A: Power Up/Down Behavior Remove ENA jumper and connect a
pulse generator (output disabled) signal to the middle pin of ENA and Ground.
Set the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to
10msec., duty cycle to 50% and fast transition (<1usec.) Hook up oscilloscope
probes to ENA, POK and V
OUT
with clean ground returns. Enable pulse generator
output. Observe the V
OUT
voltage ramps as ENA goes high and again as ENA
goes low.
STEP 8: Phase Lock Disable device by moving ENA jumper. Power down the
device. Connect a pulse generator (properly terminated and output disabled)
signal between S_IN and GND, preferably using an SMC connector. Set the
pulse amplitude to swing from 0 to 2.5 volts. Set the pulse frequency to the
converter’s free running frequency. Connect oscilloscope probes to S_IN and
S_OUT. Power up device. Enable device. Note S_OUT it is the free running
switching frequency. Now enable the pulse generator output. S_OUT should be
locked to S_IN with a fixed delay. Sweep the clock frequency and note the lock
range at both extremes.
ALWAYS power down device before changing board level components!
Page 4 of 9
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Enpirion
®
Power Evaluation Board User Guide
EN6360QI PowerSoC
Figure 4: Evaluation Board Layout Assembly Layer.
Page 5 of 9
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Enpirion
®
Power Evaluation Board User Guide
EN6360QI PowerSoC
Figure 5: Evaluation Board Schematic
C4
D1
S2A
+
C14
R12
VIN
TP27
J7
J6
J11
1206
1206
1206
1206
VFB
C1
FB1
0805
0805
0805
0805
0805
0805
R13
R14
TP30
TP31
J2
1
2
3
J3
1
2
3
TP6
J10
VOUT
M/SENA
J4
TP9
1
2
C3
TP15
TP14
R2
C8
C9
1206
TP32
C2
VINPGND
ENA
M/S
POK
VOUT PGND
C15
Provision for Implementing
Adaptive Voltage Scaling
0805
0805
C5
C6
R8
R7
R3
R6
C7
AVIN
0402
0402
J1
1
2
3
VFB
VFB
R4
SEL
TP3
0805
SEL
TP5
FADJ
XREF
0805
0805
R5
TP21
TP22
0805
SIN
SOUT
SCH 04693
PCB 04694
0402
C11
C13
C10
C12
TP19
1
2
TP20
1
2
R10
VIN
VOUT
R1
TP10
0402
TP8
TP7
J5
1
3
5
2
4
6
87
D2
TP28
BF_IN
0805
TP29
TP17
1
2
TP18
1
2
U1
EN6360Q
NC1
1
NC2
2
NC3
3
NC4
4
NC5
5
NC6
6
NC7
7
NC8
8
NC9
9
NC10
10
NC11
11
NC12
12
NC13
13
NC14
14
NC15
15
VOUT
16
VOUT
17
VOUT
18
VOUT
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
NC25
25
NC(SW)26
26
NC(SW)27
27
PGND
28
PGND
29
PGND
30
PGND
31
PGND
32
PGND
33
S_IN
48
NC47
47
NC46
46
NC45
45
NC44
44
PVIN
43
PVIN
42
PVIN
41
PVIN
40
PVIN
39
PVIN
38
PVIN
37
PVIN
36
PVIN
35
NC68
68
NC67
67
NC66
66
NC65
65
NC64
64
NC(SW)63
63
NC(SW)62
62
NC61
61
FQADJ
60
EXTREF
59
VSENSE
58
SS
57
EAOUT
56
XFB
55
M/S
54
AGND
53
AVIN
52
EN
51
POK
50
PGND
34
S_OUT
49
R9
TP11
TP12
Short across R9
when all other
routing completed
TP4
TP1
VIN
TP23
TP2
TP16
TP24
TP25
TP13
TP26
U2
Page 6 of 9
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EVB-EN6360QI

Mfr. #:
Manufacturer:
Intel / Altera
Description:
Power Management IC Development Tools EN6360QI Eval Board 8A High Eff Buck Con
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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