PESDXL2BT_SER_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 25 August 2009 9 of 14
NXP Semiconductors
PESDxL2BT series
Low capacitance double bidirectional ESD protection diodes in SOT23
Fig 9. ESD clamping test setup and waveforms
006aaa162
50
R
Z
C
Z
D.U.T.
(Device
Under
Test)
vertical scale = 200 V/div
horizontal scale = 50 ns/div
unclamped +1 kV ESD voltage waveform
(IEC 61000-4-2 network)
clamped +1 kV ESD voltage waveform
(IEC 61000-4-2 network)
unclamped 1 kV ESD voltage waveform
(IEC 61000-4-2 network)
clamped 1 kV ESD voltage waveform
(IEC 61000-4-2 network)
vertical scale = 200 V/div
horizontal scale = 50 ns/div
vertical scale = 20 V/div; horizontal scale = 50 ns/div
vertical scale = 20 V/div; horizontal scale = 50 ns/div
GND
GND
450
RG 223/U
50 coax
ESD TESTER
IEC 61000-4-2 network
C
Z
= 150 pF; R
Z
= 330
4 GHz DIGITAL
OSCILLOSCOPE
10×
ATTENUATOR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PESD3V3L2BT
PESD5V0L2BT
PESD12VL2BT
PESD15VL2BT
PESD24VL2BT
PESD3V3L2BT
PESD5V0L2BT
PESD12VL2BT
PESD15VL2BT
PESD24VL2BT
PESDXL2BT_SER_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 25 August 2009 10 of 14
NXP Semiconductors
PESDxL2BT series
Low capacitance double bidirectional ESD protection diodes in SOT23
7. Application information
The PESDxL2BT series is designed for the protection of two bidirectional signal lines from
the damage caused by ESD and surge pulses. The PESDxL2BT series may be used on
lines where the signal polarities are above and below ground. The PESDxL2BT series
provides a surge capability of up to 350 W per line for an 8/20 µs waveform.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PESDxL2BT as close to the input terminal or connector as possible.
2. The path length between the PESDxL2BT and the protected line should be
minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
Fig 10. Application diagram
006aaa163
GND
PESDxL2BT
line 2 to be protected
line 1 to be protected
PESDXL2BT_SER_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 25 August 2009 11 of 14
NXP Semiconductors
PESDxL2BT series
Low capacitance double bidirectional ESD protection diodes in SOT23
8. Package outline
9. Packing information
[1] For further information and the availability of packing methods, see Section 12.
Fig 11. Package outline SOT23 (TO-236AB)
04-11-04Dimensions in mm
0.45
0.15
1.9
1.1
0.9
3.0
2.8
2.5
2.1
1.4
1.2
0.48
0.38
0.15
0.09
12
3
Table 9. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type number Package Description Packing quantity
3000 10000
PESD3V3L2BT SOT23 4 mm pitch, 8 mm tape and reel -215 -235
PESD5V0L2BT
PESD12VL2BT
PESD15VL2BT
PESD24VL2BT

PESD12VL2BT,215

Mfr. #:
Manufacturer:
Nexperia
Description:
TVS Diodes / ESD Suppressors 12V BIDIRECTIONL ESD DUAL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union