NB7V72MMNG

© Semiconductor Components Industries, LLC, 2009
October, 2009 Rev. 1
1 Publication Order Number:
NB7V72M/D
NB7V72M
1.8V / 2.5V Differential 2 x 2
Crosspoint Switch with
CML Outputs Clock/Data
Buffer/Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB7V72M is a high bandwidth, low voltage, fully differential
2 x 2 crosspoint switch with CML outputs. The NB7V72M design is
optimized for low skew and minimal jitter as it produces two identical
copies of Clock or Data operating up to 5 GHz or 6.5 Gb/s,
respectively. As such, the NB7V72M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
The differential IN/IN
inputs incorporate internal 50 W termination
resistors and will accept LVPECL, CML, or LVDS logic levels (see
Figure 10). The 16 mA differential CML outputs provide matching
internal 50 W terminations and produce 400 mV output swings when
externally terminated with a 50 W resistor to V
CC
(see Figure 11). The
NB7V72M is the 1.8 V/2.5 V CML version of the NB7L72M and is
offered in a low profile 3x3 mm 16pin QFN package. Application
notes, models, and support documentation are available at
www.onsemi.com.
The NB7V72M is a member of the GigaComm family of high
performance clock products.
Features
Maximum Input Data Rate > 6.5 Gb/s
Data Dependent Jitter < 15 ps pkpk
Maximum Input Clock Frequency > 5 GHz
Random Clock Jitter < 0.8 ps RMS, Max
150 ps Typical Propagation Delay
30ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV peaktopeak, typical
Operating Range: V
CC
= 1.71 V to 2.625 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3mm x 3mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
NB7V
72M
ALYWG
G
16
1
IN0
SEL0
SEL1
IN0
+
+
VT0
IN1
IN1
VT1
Q0
Q0
Q1
Q1
0
1
0
1
Figure 1. Logic Diagram
1
NB7V72M
http://onsemi.com
2
VT1 SEL1 GND VCC
VT0 SEL0 GND VCC
Q0
Q0
Q1
Q1
IN0
IN0
IN1
IN1
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB7V72M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0* SEL1* Q0 Q1
L L IN0 IN0
L H IN0 IN1
H L IN1 IN0
H H IN1 IN1
*Defaults HIGH when left open
Table 2. PIN DESCRIPTION
Pin Name I/O Description
1 IN0 LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
2 IN0 LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
3 IN1 LVPECL, CML,
LVDS Input
Inverted Differential Input. (Note 1)
4 IN1 LVPECL, CML,
LVDS Input
Noninverted Differential Input. (Note 1)
5 VT1
Internal 50 W Termination Pin for IN1 and IN1
6 SEL1 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q1 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
7 GND Negative Supply Voltage
8 VCC Positive Supply Voltage
9 Q1 CML Output Noninverted Differential Output. (Note 1)
10 Q1 CML Output Inverted Differential Output. (Note 1)
11 Q0 CML Output Inverted Differential Output. (Note 1)
12 Q0 CML Output Noninverted Differential Output. (Note 1)
13 VCC Positive Supply Voltage
14 GND Negative Supply Voltage
15 SEL0 LVCMOS Input Input Select logic pin for IN0 or IN1 Inputs to Q0 output. See Table 1, Input/Output Select Truth
Table; pin defaults HIGH when left open.
16 VT0
Internal 50 W Termination Pin for IN0 and IN0
EP The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heatsinking
conduit. The pad is electrically connected to the die, and is recommended to be electrically and
thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on INx/INx
input, then the device will be susceptible to selfoscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
NB7V72M
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3
Table 3. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 4 kV
> 200 V
R
PU
Input Pullup Resistor
75k
Moisture Sensitivity 16QFN Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 210
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 3.0 V
V
IN
Positive Input Voltage GND = 0 V 0.5 to V
CC
+0.5 V
V
INPP
Differential Input Voltage |IN IN| 1.89 V
I
IN
Input Current Through R
T
(50 Resistor)
$40 mA
T
A
Operating Temperature Range 40 to +85 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) (Note 3) 0 lfpm
500 lfpm
QFN16
QFN16
42
35
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) (Note 3) QFN16 4 °C/W
T
sol
Wave Solder PbFree 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

NB7V72MMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Analog & Digital Crosspoint ICs 2X2 CROSSPOINT SWTCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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