EVAL-ADuM4121EBZ/EVAL-ADuM4121-1EBZ User Guide UG-1041
Rev. 0 | Page 3 of 5
SETTING UP THE EVAL-ADUM4121EBZ OR EVAL-ADUM4121-1EBZ
INITIAL CONFIGURATION
Before initial use, certain steps must be completed to prepare the
EVA L-ADuM4121EBZ or EVA L-ADuM4121-1EBZ evaluation
board for operation. In the stock configuration (see Figure 1),
the R1 to R4 resistors are not placed. These are the locations of
the series external resistors for the charging and discharging paths
of the device being driven. It is recommended to use 1206 surface-
mount resistors with values between approximately 1 Ω and 10 Ω,
depending on the load being driven. R1 and R2 provide to parallel
placements, while R3 and R4 are in series. An actual insulated gate
bipolar transistor (IGBT) or metal-oxide semiconductor field
effect transistor (MOSFET) can be placed in the provided Q1,
Q2, or Q3 landing patterns. Jumper P1 allows shorting across
the series external resistors to observe overshoot and/or allow
the user to probe voltage to quantify peak currents.
Resistors R6 and R7 are provided if the user desires to terminate the
inputs V
I+
and V
I−
with 50 Ω loads. R6 and R7 are not required,
and, if not placed, the evaluation board accepts high impedance
signal generator signals.
Pins accompany the screw terminals. The user decides which
connection mechanism to use. The screw terminals aid in
connecting wires for longer term measurements, but are not
recommended for placement of the devices being driven. The
distance to the screw terminals for Jumper P8 is far from the gate
driver and introduces parasitic inductances to the measurement.
Jumpers P3 and P4 allow the user to tie the V
I+
and/or V
I−
pins
to VDD1 or GND1 quickly. If using P3 and/or P4, do not attempt
to drive the pin that is jumpered by an external signal generator.
PAD LAYOUT FOR THE DEVICE UNDER TEST (DUT)
Figure 2 shows the top layer artwork for the dual-gate driver circuit.
Evaluation board components include the following:
• U1 is the footprint for the ADuM4121 or ADuM4121-1.
• C1 and C2 are 0.1 µF bypass capacitors; C3 is a 10 µF
bypass capacitor.
• Q1, Q2, and Q3 can be populated with TO-246, TO-252, or
TO-220 MOSFETs or IGBTs (see Figure 2).
• R1 to R4 are gate resistors that control the edges of the
outputs. By default, no resistors are installed; these resistors
must be populated with low value 1206 resistors, generally
in the 1 Ω to 10 Ω range.
2
C/D
1
G
3
E/S
14970-002
Figure 2. IGBT/MOSFET Footprint
POWER CONNECTIONS
Follow these steps to connect the ADuM4121 or ADuM4121-1
evaluation board to a power supply:
1. Connect the input supply (2.5 V to 5.5 V) with the positive
terminal on VDD1 and the ground on GND1.
2. Connect the ADuM4121 or ADuM4121-1 VDD2 supply
voltage (4.5 V to 35 V) to the VDD2 pin and return to the
GND2 pin.
GND1 and GND2 are isolated. The emitter/source of the
IGBT/MOSFET is tied to GND2.
INPUT/OUTPUT CONNECTIONS
The V
I+
and V
I−
pins are complementary metal oxide semicon-
ductor (CMOS) inputs. To drive the gate driver with positive
logic, tie V
I−
to GND1 and connect the input signal to the V
I+
pin. To drive the gate drive with negative logic, connect V
I+
to
VDD1, and connect the input signal to V
I−
. V
I−
can also be used
as a disable pin. By driving V
I−
high, the output remains low
regardless of the signal at the V
I+
pin.
The EVA L-ADuM4121EBZ evaluation board comes with screw
terminals for both the input and output connections. These
terminals facilitate connection options but are not the best
option for high performance transient testing. The best
measurements performed on the load, whether it is an IGBT,
MOSFET, or load capacitor, come from small loop measurements
performed at the load. Using the screw terminals as either the
sensing node or for the connection of the load often results in
observing overshoot during measurement.
