NCP1397A/B, NCV1397A/B
www.onsemi.com
23
Figure 45. A Resistor Can Easily Program the Capacitor Discharge Time
4 V
1 V
SMPS Re−starts
SMPS Stops
Reset at Re−start
Fault is Gone
Skip/Disable
FB
V
CC
Figure 46. Skip Cycle Can Be Implemented Via Two
Resistors on the FB Pin to the Fast Fault Input
Skip/Disable
The Skip/Disable input is not affected by a delayed action.
As soon as its voltage exceeds 0.66 V typical, all pulses are
off and maintained off as long as the fault is present. When
the pin is released, pulses come back and the soft−start is
activated (in case the V
FB
< 0.3 V).
Thanks to the low activation level, this pin can observe the
feedback pin via a resistive divided and thus implement skip
cycle operation. The resonant converter can be designed to
lose regulation in light load conditions, forcing the FB level
to increase. When it reaches the programmed level, it
triggers the skip input and stops pulses. Then V
out
slowly
drops, the loop reacts by decreasing the feedback level
which, in turn, unlocks the pulses, V
out
goes up again and so
on: we are in skip cycle mode. As the feedback voltage does
not drop below 0.3 V the Soft−Start discharge switch is not
activated in this case. Please refer also to Figure 35 for skip
mode function implementation when optocoupler is
connected directly to Rt pin.
Startup Behavior
When the V
CC
voltage increases, the internal current
consumption is kept below I
strup
. When V
CC
reaches the
V
CC(on)
level, output Mlower goes high first and then output
Mupper. This sequence will always be the same whatever
triggers the pulse delivery: fault, OFF to ON etc… Pulsing
the output M
lower
high first gives an immediate charge of the
bootstrap capacitor. Then, the rest of pulses follow,
delivered at the highest switching value, set by the R
Fstart
resistor in parallel with R
Fmin
resistor on Pin 4. The
soft−start capacitor ensures a smooth frequency decrease to
either the programmed minimum value (in case of fault) or
to a value corresponding to the operating point if the
feedback loop closes first. Figure 47 shows typical signals
evolution at power on.