2.5 V to 5.5 V, 500 μA, Quad Voltage Output
8-/10-/12-Bit DACs in 10-Lead Packages
Data Sheet
AD5304/AD5314/AD5324
Rev. H
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FEATURES
AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and
10-lead LFCSP
A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL
AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and
10-lead LFCSP
A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL
AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and
10-lead LFCSP
A, W Version: ±16 LSB INL, B Version: ±10 LSB INL
Low power operation: 500 µA @ 3 V, 600 µA @ 5 V
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Double-buffered input logic
Output range: 0 V to V
REF
Power-on reset to 0 V
Simultaneous update of outputs (
LDAC
function)
Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-
compatible 3-wire serial interface
On-chip, rail-to-rail output buffer amplifiers
Temperature range −40°C to +105°C
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process controls
GENERAL DESCRIPTION
The AD5304/AD5314/AD5324
1
are quad 8-, 10-, and 12-bit
buffered voltage output DACs in 10-lead MSOP and 10-lead
LFCSP packages that operate from a single 2.5 V to 5.5 V supply,
consuming 500 µA at 3 V. Their on-chip output amplifiers allow
rail-to-rail output swing to be achieved with a slew rate of 0.7 V/µs.
A 3-wire serial interface is used; it operates at clock rates up to
30 MHz and is compatible with standard SPI, QSPI, MICROWIRE,
and DSP interface standards.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs can be updated simultaneously using
the software
LDAC
function. The parts incorporate a power-on
reset circuit, and ensure that the DAC outputs power up to 0 V
and remains there until a valid write takes place to the device.
The parts contain a power-down feature that reduces the current
consumption of the device to 200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.
1
Protected by U.S. Patent No. 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
V
OUT
A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
V
OUT
B
BUFFER
AD5304/AD5314/AD5324
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
V
OUT
C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
V
OUT
D
BUFFER
REFIN
DD
GND
POWER-DOWN LOGICPOWER-ON RESET
LDAC
INTERFACE
LOGIC
SCLK
SYNC
DIN
00929-001
Figure 1.
