AD5304/AD5314/AD5324 Data Sheet
Rev. H | Page 16 of 24
Double-Buffered Interface
The AD5304/AD5314/AD5324 DACs have double-buffered inter-
faces consisting of two banks of registers—input registers and
DAC registers. The input register is directly connected to the input
shift register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.
Access to the DAC register is controlled by the
LDAC
bit. When
the
LDAC
bit is set high, the DAC register is latched and hence
the input register can change state without affecting the contents of
the DAC register. However, when the
LDAC
bit is set low, all DAC
registers are updated after a complete write sequence.
This is useful if the user requires simultaneous updating of all
DAC outputs. The user can write to three of the input registers
individually and then, by setting the
LDAC
bit low when
writing to the remaining DAC input register, all outputs
update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that
LDAC
was brought low. Normally, when
LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5304/AD5314/AD5324,
the part updates the DAC register only if the input register has
been changed since the last time the DAC register was updated,
thereby removing unnecessary digital crosstalk.
POWER-DOWN MODE
The AD5304/AD5314/AD5324 have low power consumption,
dissipating only 1.5 mW with a 3 V supply and 3 mW with a
5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down mode,
selected by a 0 on Bit 13 (
PD
) of the control word.
When the
PD
bit is set to 1, all DACs work normally with a typical
power consumption of 600 A at 5 V (500 A at 3 V). However, in
power-down mode, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when all DACs are powered down. Not only does
the supply current drop, but also the output stage is internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the output is three-stated while the
part is in power-down mode, and provides a defined input
condition for whatever is connected to the output of the DAC
amplifier. The output stage is illustrated in Figure 35.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the power-
down mode is activated. However, the contents of the registers
are unaffected when in power-down. The time to exit power-down
is typically 2.5 s for V
DD
= 5 V and 5 s when V
DD
= 3 V. This is
the time from the falling edge of the 16
th
SCLK pulse to when
the output voltage deviates from its power down voltage. See
Figure 22 for a plot.
RESISTOR
STRING DAC
A
MPLIFIE
R
V
OUT
POWER-DOWN
CIRCUITRY
0
0929-035
Figure 35. Output Stage during Power-Down
MICROPROCESSOR INTERFACING
AD5304/AD5314/AD5324 to ADSP-21xx
Figure 36 shows a serial interface between the AD5304/AD5314/
AD5324 and the ADSP-21xx family. The ADSP-21xx is set up
to operate in the SPORT transmit alternate framing mode. The
ADSP-21xx sport is programmed through the SPORT control
register and must be configured as follows: internal clock operation,
active-low framing, and 16-bit word length. Transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. The data is clocked out on each rising edge of
the DSP’s serial clock and clocked into the AD5304/AD5314/
AD5324 on the falling edge of the DAC’s SCLK.
AD5304/
AD5314/
AD5324*
ADSP-21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DIN
DT
SCLKSCLK
SYNCTFS
0
0929-036
Figure 36. AD5304/AD5314/AD5324 to ADSP-21xx Interface
Data Sheet AD5304/AD5314/AD5324
Rev. H | Page 17 of 24
AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
Figure 37 shows a serial interface between the AD5304/AD5314/
AD5324 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5304/AD5314/AD5324,
while the MOSI output drives the serial data line (DIN) of the
DAC. The
SYNC
signal is derived from a port line (PC7). The
setup conditions for the correct operation of this interface are as
follows: the 68HC11/68L11 is configured so that its CPOL bit is
a 0 and its CPHA bit is a 1. When data is being transmitted to the
DAC, the
SYNC
line is taken low (PC7). When the 68HC11/68L11
is configured as above, data appearing on the MOSI output is
valid on the falling edge of SCK. Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the AD5304/ AD5314/AD5324, PC7 is left
low after the first eight bits are transferred, a second serial write
operation is performed to the DAC, and PC7 is taken high at
the end of this procedure.
AD5304/
AD5314/
AD5324*
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SCK
DINMOSI
SYNCPC7
0
0929-037
Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
AD5304/AD5314/AD5324 to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5304/AD5314/AD5324, while RxD drives the serial
data line of the part. The
SYNC
signal is again derived from a
bit-programmable pin on the port. In this case, port line P3.3 is
used. When data is to be transmitted to the AD5304/AD5314/
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in a format that has the LSB first. The AD5304/
AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine takes this into
account.
AD5304/
AD5314/
AD5324*
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
TxD
DINRxD
SYNCP3.3
0
0929-038
Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface
AD5304/AD5314/AD5324 to MICROWIRE Interface
Figure 39 shows an interface between the AD5304/AD5314/
AD5324 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5304/AD5314/AD5324 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
AD5304/
AD5314/
AD5324*
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SK
DINSO
SYNCCS
0
0929-039
Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface
AD5304/AD5314/AD5324 Data Sheet
Rev. H | Page 18 of 24
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
The AD5304/AD5314/AD5324 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0 V to V
DD
.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780 and REF192 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589, a 1.23 V band
gap reference. Figure 40 shows a typical setup for the AD5304/
AD5314/AD5324 when using an external reference.
AD5304/AD5314/
AD5324
V
DD
= 2.5V TO 5.5
SCLK
REFIN
DIN
SYNC
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
GNDA0
SERIAL
INTERFACE
V
OUT
V
IN
EXTERNAL
REFERENCE
AD790/REF192
WITH V
DD
= 5V
OR AD589 WITH
V
DD
= 2.5V
1µF
0.1µF 10µF
00929-040
Figure 40. AD5304/AD5314/AD5324 Using External Reference
If an output range of 0 V to V
DD
is required, the simplest solution is
to connect the reference input to V
DD
. As this supply is not very
accurate and can be noisy, the AD5304/AD5314/AD5324 can
be powered from the reference voltage; for example, using a 5 V
reference such as the REF195. The REF195 can output a steady
supply voltage for the AD5304/AD5314/AD5324. The current
required from the REF195 is 600 A supply current and approxi-
mately 112 A into the reference input. This is with no load on
the DAC outputs. When the DAC outputs are loaded, the REF195
also needs to supply the current to the loads. The total current
required (with a 10 k load on each output) is
712 A + 4 (5 V/10 k) = 2.70 mA
The load regulation of the REF195 is typically 2 ppm/mA, resulting
in an error of 5.4 ppm (27 V) for the 2.7 mA current drawn from
it. This corresponds to a 0.0014 LSB error at eight bits and
0.022 LSB error at 12 bits.
Bipolar Operation Using the AD5304/AD5314/AD5324
The AD5304/AD5314/AD5324 have been designed for single
supply operation, but a bipolar output range is also possible
using the circuit in Figure 41. This circuit gives an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
AD5304
REFIN
GND
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
SERIAL
INTERFACE
DIN SCLK SYNC
V
OUT
V
IN
GND
REF195
1µF
0.1µF10µF
+6V TO +16V
V
DD
+5V
–5V
±5V
+5V
AD820/
OP295
R1 = 10k
R2 = 10k
0
0929-041
Figure 41. Bipolar Operation with the AD5304
The output voltage for any input code can be calculated as follows:
)1/2(
)()2/(
RRREFIN
R1
R2R1DREFIN
V
N
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input:
REFIN = 5 V, R1 = R2 = 10 k
V
OUT
= (10 × D/2
N
) − 5 V

AD5314ARMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 10-BIT QUAD IC
Lifecycle:
New from this manufacturer.
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