LTC2946HDE#TRPBF Datasheet LTC2946IMS#PBF, LTC2946HDE#PBF, LTC2946HMS#PBF | P16-P18

LTC2946

2946fa

For more information www.linear.com/LTC2946

Figure 5

monitor with an input monitoring range beyond 100V in a

high side shunt regulator configuration. The device ground

is separated from ground through R

SHUNT

and clamped at

6.3V below the input supply. Note that due to the different

ground levels, the I

C signals from the part need to be level

shifted for communication with other ground referenced

components. The bus voltage is measured with a resistor

string connected to ADIN. Set CA[7] in the CTRLA register

so that the ADC measures ADIN with reference to INTV

instead of GND. The measurement range at ADIN is then

from INTV

to INTV

– 2.048V.

Figure 5b shows a high side rail-to-rail power monitor

which derives power from a secondary supply greater

than 100V. The voltage at INTV

is clamped at 6.3V

above ground in a low side shunt regulator configuration

to power the part. In low side power monitors, the device

ground and the current sense inputs are connected to the

negative terminal of the input supply as shown in Figure

5c. The low side shunt regulator configuration allows

operation with input supplies above 100V by clamping

the voltage at INTV

. R

SHUNT

should be sized according

to the following equation:

S(MAX)

− V

CCZ(MIN)

CC(ABSMAX)

≤ R

SHUNT

≤

S(MIN)

− V

CCZ(MAX)

CC(MAX)

LOAD(MAX)

S(MAX)

− 5.8V

35mA

≤ R

SHUNT

≤

S(MIN)

− 6.7V

1mA +I

LOAD(MAX)

(1)

where V

S(MAX)

and V

S(MIN)

are the operating maximum

and minimum limits of the supply. I

LOAD(MAX)

is the maxi-

mum external

current load that is connected to the shunt

regulator. The shunt resistor must also be rated to safely

APPLICATIONS INFORMATION

(5c) LTC2946 Derives Power Through a Low Side Shunt

Regulator in a Low Side Current Sense Topology

(5d) LTC2946 Derives Power from the Supply Monitored

in a Low Side Current Sense Topology

(5a) LTC2946 Derives Power Through a High Side

Shunt Regulator

(5b) LTC2946 Derives Power Through a Low Side Shunt

Regulator in a High Side Current Sense Topology

SENSE

–

ADIN

INTV

LTC2946

GND

OUT

SNS

>100V

2946 F05a

SHUNT

SENSE

–

INTV

LTC2946

GND

OUT

SNS

SHUNT

0V TO 100V

>100V

2946 F05b

SENSE

–

SENSE

ADIN

INTV

LTC2946

OUT

SNS

> –100V

2946 F05c

GND

SHUNT

SENSE

–

INTV

LTC2946

OUT

SNS

NEG

(–4V TO –100V)

2946 F05d

GND

LTC2946

2946fa

For more information www.linear.com/LTC2946

dissipate the worst-case power. As an example, consider

the –48V telecom system where the supply operates from

–36V to –72V and the shunt regulator is used to supply

an external load up to 4mA. R

SHUNT

needs to be between

1.9k and 5.9k according to the previous equation, and for

reduced power dissipation, a larger resistance is advan

tageous. The worst-case power dissipated in an R

SHUNT

of 5.36k is calculated to be 0.8W. Three 0.5W rated 1.8k

resistors in series would suffice for this example.

If the supply input is below 100V, the shunt resistor is not

required and V

can be connected to GND of the supply

as shown in Figure 5d.

Supply Undervoltage Lockout

During power-up, the internal I

C logic and the ADC are

enabled when either V

or INTV

rises above its under-

voltage lockout

threshold. During power-down, the ADC is

disabled when V

and INTV

fall below their respective

undervoltage lockout thresholds. The internal I

C logic is

reset when V

and INTV

fall below their respective I

reset thresholds.

Shutdown Mode

The LTC2946 includes a low quiescent current shutdown

mode, controlled by bit CB[6]

in the CTRLB register

able 4). Setting CB[6] puts the part in shutdown mode,

powering down the ADC, internal reference and onboard

linear regulator. The internal I

C bus remains active,

and although the ADR1 and ADR0 pins are disabled, the

device will retain the most recently programmed I

C bus

address. All onboard registers retain their contents and

can be accessed through the I

C interface. To re-enable

ADC conversions, reset bit CB[6] in the CTRLB register.

The analog circuitry will power up and all registers will

retain their contents.

The onboard linear regulator is disabled in shutdown mode

to conserve power. If the onboard linear regulator is used

to power external I

C bus related circuitry such as opto-

couplers or pull-ups, I

C communication will be lost when

the part is shut down. The LTC2946 would then have to

be reset by cycling its power to come out of shutdown. If

low I

mode is not required, ensure bit CB[6] in the CTRLB

recommended that external regulators be used in such

applications if powering down the LTC2946 is desirable.

As an added layer of protection

against this scenario, bit

CB[4]

in the CTRLB register can be set during system

configuration to enable the LTC2946 to automatically exit

shutdown mode when the I

C lines are low for more than

33ms (which can be a result of accidental shutdown of the

LTC2946’s linear regulator powering the I

C). The user

can elect to be alerted of this event by setting bit AL2[3]

in the ALERT2 register (Table 8). Quiescent current drops

below 40μA in shutdown mode with the internal regulator

disabled.

Configuring the GPIO Pins

The LTC2946 has three GPIO pins configurable through

the GPIO_CFG register (Table 9) to be used as general

purpose input/output pins. As general purpose inputs,

GPIO1 through GPIO3 can be either active HIGH or LOW.

In addition, GPIO2 can also be used as an accumulation

enable input by writing bits CB[3:2] = [10] to allow integra

tion of the time counter, charge and energy accumulators.

GPIO1 through GPIO3 have comparators monitoring the

voltage on these pins with a threshold of 1.22V, the results

of which may be read from bits S2[6:4] in the STATUS2

when GPIO1 or GPIO2 are active as

inputs by setting bits

AL2[6]

and AL2[5], respectively, in the ALERT2 register.

GPIO1-3 can be pulled low as general purpose outputs,

which are otherwise high impedance. GPIO3 is by default

an ALERT output that pulls low when an alert event is

present. To pull GPIO3 (ALERT) low in the absence of an

alert event, set GC[7] of the GPIO3_CTRL register (Table

12). Clearing this bit will release the GPIO3 (ALERT). GC[7]

does not have an effect on GPIO3 if it is not configured as

an ALERT output. Likewise, GC[6] does not affect GPIO3

if it is not configured as a general purpose output. GC[7]

is set whenever an alert event occurs irrespective of

GPIO3's configuration. Reset GC[7] before reconfiguring

GPIO3 to ALERT.

APPLICATIONS INFORMATION

LTC2946

2946fa

For more information www.linear.com/LTC2946

C Reset

The accumulators can be programmed to reset themselves

after the host reads the last byte (3Fh) of the accumulator

data by writing bits CB[1:0] to [01] in the CTRLB register

(Table 4). This feature removes the need to issue a reset

command after polling the LTC2946 for accumulated data.

The accumulators will continue to accumulate after the

reset. To reset the accumulators without such read com

mand, write

bits CB[1:0] to [10]. The accumulators will

stay

reset if CB[1:0] = [10]. All registers are reset when

CB[1:0] = [11], and these bits will then auto-reset to [00].

The ADC sequencing configuration is preserved through

the I

C reset, regardless of the CTRLA register having

reset. To change the sequencing configuration after such

resets, rewrite the CTRLA register.

Storing Minimum and Maximum Values

The LTC2946 compares each measurement including the

calculated power with the stored values in the respective

MIN and MAX registers for each parameter (Table 2). If

the new conversion is beyond the stored minimum or

maximum values, the MIN or MAX registers are updated

with the new values. The MIN and MAX of the registers

are refreshed at the end of their respective ADC conver

sions i

n continuous scan modes and snapshot mode. They

are

also refreshed if the ADC registers are written via the

C bus with values beyond the stored values. To initiate

a new peak hold cycle, write all 1’s to the MIN registers

and all 0’s to the MAX registers via the I

C bus. These

registers will be updated when the next respective ADC

conversion is done.

The LTC2946 also includes MIN and MAX threshold reg

isters (Table 2) for the

measured parameters including the

calculated power. At power-up, the maximum thresholds

are set to all 1’s, and minimum thresholds are set to all

0’s, effectively disabling them. The thresholds can be

reprogrammed to any desired value via the I

C bus.

Fault Alert and Resetting Faults

As soon as a measured quantity falls below the minimum

threshold or exceeds the maximum threshold, the LTC2946

sets the corresponding flag in the STATUS1 (Table 6) reg

ister and

latches it into the FA

ULT1 (Table 7) register (see

Figure 6). Other events such as GPIO state change, stuck

bus wake-up and accumulator overflow have their present

status in the STATUS2 (Table 10) register and any fault is

latched in the FAULT2 (Table 11) register. The GPIO3 pin

pulled low if the appropriate bit in the ALERT1 (Table 5)

and

ALERT2 (Table 8) registers is set and it is configured

as ALERT output. More details on the alert behavior can

be found in the Alert Response Protocol section.

An active fault indication can be reset by writing zeros

to the corresponding FAULT register bits or setting bit

CB[5] in the CTRLB register. If bit CB[5] is set, reading the

FAULT1 or FAULT2 register will cause the corresponding

if the V

and INTV

fall below their respective I

C logic

reset threshold. Note that faults that are still present, as

indicated in the STATUS1 and STATUS2 registers, will

immediately reappear.

When accumulators (time, charge and energy) overflow,

the corresponding bits in the STATUS2 register are set

and will stay set. The accumulator overflow bits in the

FAULT2 register will reappear after they have been cleared

via I

C since the STATUS2 register continues to indicate

overflow faults.

APPLICATIONS INFORMATION

Figure 6. LTC2946 Fault Alert Generation Blocks

DIGITAL

COMPARATOR

LOGIC

LATCH

STATUS

RESET

FAULT

ALERT

ENA_ALERT_RESPONSE

MEASURED

DATA

THRESHOLD

DATA

2946 F06

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LTC2946HDE#TRPBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Current Sense Amplifiers Wide Rng I2C Pwr, Ch & Energy Mon

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LTC2946HDE#TRPBF

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