MC100H642FNR2G

MC10H642, MC100H642
http://onsemi.com
4
Table 5. 10H/100H TTL DC CHARACTERISTICS (V
T
= V
E
= 5.0 V ±5%)
Symbol Characteristic Condition
T
A
= 0°C T
A
= 25°C T
A
= 85°C
Unit
Min Max Min Max Min Max
V
IH
V
IL
Input HIGH Voltage
Input LOW Voltage
2.0
0.8
2.0
0.8
2.0
0.8
V
I
IH
Input HIGH Current V
IN
= 2.7 V
V
IN
= 7.0 V
20
100
20
100
20
100
mA
I
IL
Input LOW Current V
IN
= 0.5 V 0.6 0.6 0.6 mA
V
OH
Output HIGH Voltage I
OH
= 3.0 mA
I
OH
= 15 mA
2.5
2.0
2.5
2.0
2.5
2.0
V
V
OL
Output LOW Voltage I
OL
= 24 mA 0.5 0.5 0.5 V
V
IK
Input Clamp Voltage I
IN
= 18 mA 1.2 1.2 1.2 V
I
OS
Output Short Circuit Current V
OUT
= 0 V 100 225 100 225 100 225 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. AC CHARACTERISTICS (V
T
= V
E
= 5.0 V ±5%)
T
A
= 0°C T
A
= 25°C T
A
= 85°C
Symbol Characteristic Condition Min Max Min Max Min Max Unit
t
PLH
Propagation Delay
D to Output
Q2Q7
C ECL
C TTL
CL = 25 pF
4.70
4.70
5.70
5.70
4.75
4.75
5.75
5.75
4.60
4.50
5.60
5.50
ns
tskpp ParttoPart Skew 1.0 1.0 1.0 ns
tskwd* WithinDevice Skew 0.5 0.5 0.5 ns
t
PLH
Propagation Delay
D to Output
Q0, Q1
C ECL
C TTL
CL = 25 pF
4.30
4.30
5.30
5.30
4.50
4.50
5.50
5.50
4.25
4.25
5.25
5.25
ns
tskpp ParttoPart Skew All
Outputs
CL = 25 pF 2.0 2.0 2.0 ns
tskwd WithinDevice Skew CL = 25 pF 1.0 1.0 1.0 ns
t
PD
Propagation Delay
R to Output
All
Outputs
CL = 25 pF 4.3 6.3 4.0 6.0 4.5 6.5 ns
t
R
t
F
Output Rise/Fall Time
0.8 V to 2.0 V
All
Outputs
CL = 25 pF 2.5
2.5
2.5
2.5
2.5
2.5
ns
f
MAX
** Maximum Input Frequency CL = 25 pF 100 100 100 MHz
RPW Reset Pulse Width 1.5 1.5 1.5 ns
RRT Reset Recovery Time 1.25 1.25 1.25 ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
* WithinDevice Skew defined as identical transactions on similar paths through a device.
**MAX Frequency is 135 MHz.
MC10H642, MC100H642
http://onsemi.com
5
Figure 3. MC10H642 Positive PW versus Load
@ ±5% V
CC
, T
A
= 25°C
5.25
5.00
4.75
11
10
9
0 102030405060
CAPACITIVE LOAD (pF)
POSITIVE PULSE WIDTH (ns)
CAPACITIVE LOAD (pF)
Figure 4. MC10H642 Negative PW versus Load
@ ±5% V
CC
, T
A
= 25°C
5.25
5.00
4.75
11
10
9
0 1020 30405060
NEGATIVE PULSE WIDTH (ns)
CAPACITIVE LOAD (pF)
Figure 5. MC10H642 Positive PW versus Load
@ ±2.5% V
CC
, T
A
= 25°C
5.125
5.00
4.875
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
0 102030405060
POSITIVE PULSE WIDTH (ns)
CAPACITIVE LOAD (pF)
Figure 6. MC10H642 Negative PW versus Load
@ ±2.5% V
CC
, T
A
= 25°C
5.125
5.00
4.875
10.8
10.6
10.4
10.2
10.0
9.8
9.6
9.4
0 102030405060
NEGATIVE PULSE WIDTH (ns)
TEMPERATURE (°C)
Figure 7. MC10H642 Positive PW versus Temperature,
V
CC
= 5.0 V
50 pF
25 pF
0 pF
10.4
10.2
10.0
9.8
9.6
9.4
0 20406080100
POSITIVE PULSE WIDTH (ns)
Figure 8. MC10H642 Negative PW versus
Temperature, V
CC
= 5.0 V
50 pF
25 pF
0 pF
10.5
10.3
10.1
9.9
9.7
9.5
0 20 40 60 80 100
TEMPERATURE (°C)
NEGATIVE PULSE WIDTH (ns)
10/100H642 DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures
1 and 2. For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature.
Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single mP load and minimum line length.
MC10H642, MC100H642
http://onsemi.com
6
CAPACITIVE (pF)
Figure 9. MC10H642 + Tpd versus Load, V
CC
±5%, T
A
= 25°C
(Overshoot at 50 MHz with no load makes graph non linear)
5.25
5.00
4.75
6.2
6.0
5.8
5.6
5.4
5.2
0 102030405060
Tpd (ns)
Figure 10. Clock Phase and Reset Recovery Time After Reset Pulse
RESET, R
DT
MC10/100H642
Q0 Q1
Q2 Q7
R
t
pw
R
t
rec
MC10/100H642
Figure 11.
Outputs
Q4 & Q5
Q0.Q1
D
in
Q2 Q7
Q2 Q7 will Synchronize with Pos Edges of D
in
& Q0 Q1
After Power Up

MC100H642FNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution ECL/TTL Clock Driver
Lifecycle:
New from this manufacturer.
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