Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00J
03/03/09
IS42S32400B
CKE DQM
Function n-1 n U L
Data write / output enable H × L L
Data mask / output disable H × H H
Upper byte write enable / output enable H × L ×
Lower byte write enable / output enable H × × L
Upper byte write inhibit / output disable H × H ×
Lower byte write inhibit / output disable H × × H
CKE A11
Function n – 1 n
CSCS
CSCS
CS
RASRAS
RASRAS
RAS
CASCAS
CASCAS
CAS
WEWE
WEWE
WE BA1 BA0 A10 A9 - A0
Device deselect (DESL) H × H ×××× × ××
No operation (NOP) H × L H H H × × × ×
Burst stop (BST) H × L H H L × × × ×
Read H × L H L H V V L V
Read with auto precharge H × L H L H V V H V
Write H × L H L L V V L V
Write with auto precharge H × L H L L V V H V
Bank activate (ACT) H × L L H H V V V V
Precharge select bank (PRE) H × L L H L V V L ×
Precharge all banks (PALL) H × L L H L × × H ×
CBR Auto-Refresh (REF) H H L L L H × × × ×
Self-Refresh (SELF) H L L L L H × × × ×
Mode register set (MRS) H × L LLLL L LV
COMMAND TRUTH TABLE
DQM TRUTH TABLE
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
Note: H=V
IH, L=VIL x= VIH or VIL, V = Valid Data.
8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
PRELIMINARY INFORMATION Rev. 00J
03/03/09
IS42S32400B
CKE
Current State /Function n 1 n CS RAS CAS WE Address
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend mode exit L H × × × × ×
Auto refresh command Idle (REF) H H L L L H ×
Self refresh entry Idle (SELF) H L L L L H ×
Power down entry Idle H L × × × × ×
Self refresh exit L H L H H H ×
LH H × ×× ×
Power down exit L H × × × × ×
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data.
CKE TRUTH TABLE
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
9
PRELIMINARY INFORMATION Rev. 00J
03/03/09
IS42S32400B
Current State
CSCS
CSCS
CS
RAS RAS
RAS RAS
RAS
CASCAS
CASCAS
CAS
WEWE
WEWE
WE Address Command Action
Idle H X X X X DESL Nop or Power Down
(2)
L H H H X NOP Nop or Power Down
(2)
L H H L X BST Nop or Power Down
L H L H BA, CA, A10 READ/READA ILLEGAL
(3)
L H L L A, CA, A10 WRIT/ WRITA ILLEGAL
(3)
L L H H BA, RA ACT Row activating
L L H L BA, A10 PRE/PALL Nop
L L L H X REF/SELF Auto refresh or Self-refresh
(4)
L L L L OC, BA1=L MRS Mode register set
Row Active H X X X X DESL Nop
LHHH X NOP Nop
LHHL X BST Nop
L H L H BA, CA, A10 READ/READA Begin read
(5)
L H L L BA, CA, A10 WRIT/ WRITA Begin write
(5)
L L H H BA, RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL Precharge
Precharge all banks
(6)
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Read H X X X X DESL Continue burst to end to
Row active
L H H H X NOP Continue burst to end Row
Row active
L H H L X BST Burst stop, Row active
L H L H BA, CA, A10 READ/READA Terminate burst,
begin new read
(7)
L H L L BA, CA, A10 WRIT/WRITA Terminate burst,
begin write
(7,8)
L L H H BA, RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL Terminate burst
Precharging
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write H X X X X DESL Continue burst to end
Write recovering
L H H H X NOP Continue burst to end
Write recovering
L H H L X BST Burst stop, Row active
L H L H BA, CA, A10 READ/READA Terminate burst, start read :
Determine AP
(7,8)
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write :
Determine AP
(7)
L L H H BA, RA RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL Terminate burst Precharging
(9)
L L L H X REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
FUNCTIONAL TRUTH TABLE
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code

IS42S32400B-6TL

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 86TSOP II
Lifecycle:
New from this manufacturer.
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