2013-2016 Microchip Technology Inc. DS20005229C-page 7
93AA46AE48
2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle is
identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the Ready/Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
V
CC must be 4.5V for proper operation of ERAL.
FIGURE 2-2: ERAL TIMING
Note: After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
CS
CLK
DI
DO
T
CSL
Check Status
10010x
•••
x
T
SV TCZ
Busy Ready
High Z
T
EC
High-Z
Note: VCC must be 4.5V for proper operation of ERAL.
93AA46AE48
DS20005229C-page 8 2013-2016 Microchip Technology Inc.
2.6 Erase/Write Disable and Enable
(EWDS/EWEN)
The 93AA46AE48 powers up in the Erase/Write
Disable (EWDS) state. All programming modes must
be preceded by an Erase/Write Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS
instruction is executed or Vcc is removed from the
device.
To protect against accidental data disturbance, the
EWDS instruction can be used to disable all erase/write
functions and should follow all programming
operations. Execution of a READ instruction is
independent of both the EWEN and EWDS instructions.
FIGURE 2-3: EWDS TIMING
FIGURE 2-4: EWEN TIMING
2.7 Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit output string.
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
PD).
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
CS
CLK
DI
10
000x
•••
x
TCSL
1x
CS
CLK
DI
00 1 1x
TCSL
•••
2013-2016 Microchip Technology Inc. DS20005229C-page 9
93AA46AE48
FIGURE 2-5: READ TIMING
2.8 Write
The WRITE instruction is followed by eight bits of data,
which are written into the specified address. For
93AA46AE48, after the last data bit is clocked into DI,
the falling edge of CS initiates the self-timed auto-erase
and programming cycle.
The DO pin indicates the Ready/Busy
status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-6: WRITE TIMING
CS
CLK
DI
DO
110
A
N
••• A0
High Z
0 Dx
•••
D0 Dx
•••
D0
•••
Dx D0
Note: After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/Busy status from DO.
CS
CLK
DI
DO
1
0
1 A
N
•••
A0 Dx
•••
D0
Busy
Ready
High Z
High Z
TWC
TCSL
TCZ
TSV

93AA46AE48-I/SN

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 128 X 8 SERIAL EE 1K EUI48, IND
Lifecycle:
New from this manufacturer.
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