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MC74VHCT245AMELG

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 7
1 Publication Order Number:
MC74VHCT245A/D
MC74VHCT245A
Octal Bus Transceiver
The MC74VHCT245A is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
It is intended for two−way asynchronous communication between
data buses. The direction of data transmission is determined by the
level of the DIR input. The output enable pin (OE
) can be used to
disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static
discharge.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT245A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
Features
• High Speed: t
PD
= 4.9 ns (Typ) at V
CC
= 5.0 V
• Low Power Dissipation: I
CC
= 4 mA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 4.5 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 1.6 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 304 FETs or 76 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
APPLICATION NOTES
• Do not force a signal on an I/O pin when it is an active output,
damage may occur.
• All floating (high impedance) input or I/O pins must be fixed by
means of pullup or pulldown resistors or bus terminator ICs.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
20
1
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
VHCT
245A
ALYWG
G
1
1
20
1
VHCT245A
AWLYYWWG
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
MC74VHCT245A
http://onsemi.com
2
Figure 1. Logic Diagram
A
DATA
PORT
A8
A7
A6
A5
A3
A4
A2
A1
9
8
7
6
5
4
3
2
DIR
OE
1
19
18
17
16
15
14
13
12
11
B1
B2
B3
B4
B5
B6
B7
B8
B
DATA
PORT
Figure 2. Pin Assignment
A5
A3
A2
A1
DIR
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
B3
B2
B1
OE
V
CC
B8
B7
B6
B5
B4
OE DIR Operation
L
L
H
L
H
X
Data Tx from Bus B to Bus A
Data Tx from Bus A to Bus B
Buses Isolated (High−Z State)
Control Inputs
FUNCTION TABLE
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
I/O
DC Output Voltage Outputs in 3−State
High or Low State
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current − 20 mA
I
OK
Output Diode Current (V
OUT
< GND; V
OUT
> V
CC
) ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating − SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 4.5 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
I/O
DC Output Voltage Outputs in 3−State
High or Low State
0
0
5.5
V
CC
V
T
A
Operating Temperature − 40 + 85
_C
t
r
, t
f
Input Rise and Fall Time V
CC
=5.0V ±0.5V 0 20 ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHCT245A
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3
DC ELECTRICAL CHARACTERISTICS
Symbo
l
Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Min Typ Max Min Max
V
IH
Minimum High−Level Input
Voltage
4.5 to 5.5 2.0 2.0 V
V
IL
Maximum Low−Level Input
Voltage
4.5 to 5.5 0.8 0.8 V
V
OH
Minimum High−Level Output
Voltage V
in
= V
IH
or V
IL
I
OH
= − 50mA
4.5 4.4 4.5 4.4 V
I
OH
= − 8mA 4.5 3.94 3.80
V
OL
Maximum Low−Level Output
Voltage V
in
= V
IH
or V
IL
I
OL
= 50mA
4.5 0.0 0.1 0.1 V
I
OL
= 8mA 4.5 0.36 0.44
I
in
Maximum Input Leakage Current V
in
= 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0
mA
I
OZ
Maximum 3−State Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ±
0.25
± 2.5
mA
I
CC
Maximum Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 4.0 40.0
mA
I
CCT
Quiescent Supply Current Per Input: V
IN
= 3.4V
Other Input: V
CC
or GND
5.5 1.35 1.50 mA
I
OPD
Output Leakage Current V
OUT
= 5.5V 0 0.5 5.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbo
l
Parameter Test Conditions
T
A
= 25°C T
A
= − 40 to 85°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay
A to B or B to A
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
4.9
5.4
7.7
8.7
1.0
1.0
8.5
9.5
ns
t
PZL
,
t
PZH
Output Enable Time
OE
to A or B
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kW C
L
= 50pF
9.4
9.9
13.8
14.8
1.0
1.0
15.0
16.0
ns
t
PLZ
,
t
PHZ
Output Disable Time
OE
to A or B
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kW
10.1 15.4 1.0 16.5 ns
t
OSLH
,
t
OSHL
Output to Output Skew V
CC
= 5.0 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum 3−State Output
Capacitance (Output in
High−Impedance State)
13 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
16
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
− t
PLHn
|, t
OSHL
= |t
PHLm
− t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/8 (per bit). C
PD
is used to determine the no−load
dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50pF, V
CC
= 5.0V)
Symbo
l
Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
1.2 1.6 V
V
OLV
Quiet Output Minimum Dynamic V
OL
−1.2 −1.6 V
V
IHD
Minimum High Level Dynamic Input Voltage 2.0 V
V
ILD
Maximum Low Level Dynamic Input Voltage 0.8 V
P1-P3P4-P6P7-P7

MC74VHCT245AMELG

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Manufacturer:
ON Semiconductor
Description:
Bus Transceivers LOG CMOS TRNSCIEVR OCTAL
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