7
FN7435.9
December 9, 2015
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C
1
can remain as low as 10µF.
The RMS current present at the input capacitor is decided by
Equation 3:
This is about half of the output current I
O
for all the V
O
. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
• L is the inductance
•f
S
the switching frequency (nominally 1.5MHz)
The inductor must be able to handle I
O
for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 3A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C
4
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C
4
should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow Equation 5:
Over a normal range of R
2
(~10k to 100k), C
4
will range
from ~470pF to 4700pF. The pole frequency cannot be set
once the zero frequency is chosen as it is dictated by the
ratio of R
1
and R
2
, which is solely determined by the desired
output set point. Equation 6 shows the pole frequency
relationship:
Thermal Shut-Down
Once the junction reaches about +145°C, the regulator shuts
down. Both the P-Channel and the N-Channel MOSFETs
turn off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about +130°C, the
regulator will restart again in the same manner as the EN pin
connects to logic HI.
Thermal Performance
The EL7532 is in a fused-lead MSOP10 package. Compared
to the regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The typical
JA
of
+115°C/W (See Thermal Information section in spec table)
can be improved by maximizing the copper area around the
pins. A
JA
of +100°C/W can be achieved on a 4-layer board
and +125°C/W on a 2-layer board. Refer to Intersil’s Tech
Brief, TB379, for more information on thermal resistance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the pins
• Place the input capacitor as close to V
IN
and PGND pins
as possible
• Make the following PC traces as small as possible:
- from L
X
pin to L
- from C
O
to PGND
• If used, connect the trace from the FB pin to R
1
and R
2
as
close as possible
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7532 Application Brief.
I
INRMS
V
O
V
IN
- V
O
V
IN
------------------------------------------------
I
O
=
(EQ. 3)
I
IL
V
IN
- V
O
V
O
LV
IN
f
S
--------------------------------------------
=
(EQ. 4)
f
Z
1
2R
2
C
4
----------------------
=
(EQ. 5)
f
P
1
2 R
1
R
2
C
4
---------------------------------------
=
(EQ. 6)
EL7532
