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KSZ8091RNB-EVAL

P1-P3P4-P6P7-P9P10-P12P13-P13
KSZ8081RNB / KSZ8091RNB 10Base-T/100Base-TX Evaluation Board User’s Guide
Micrel, Inc. August 15, 2012
Rev. 1.0
7/13
4.1 RMII (Reduced Media Independent Interface)
The KSZ8081RNB-EVAL / KSZ8091RNB-EVAL receives power and accesses RMII data and
management information from the MII connector J2. Figure 2 shows the KSZ8081RNB-EVAL /
KSZ8091RNB-EVAL connected to the Micrel KSZ8463RLI Evaluation Board.
Figure 2. KSZ8081RNB-EVAL interfacing with KSZ8463RLI Evaluation Board
Two RMII clocking modes are available with the KSZ8081RNB / KSZ8091RNB. It may utilize the
on-board 25 MHz crystal, connected to XI / XO, and output a 50 MHz REF_CLK signal which is
an input to the MAC device to which it is connected. REF_CLK drives pin 9 of the MII connector
J2. This is referred to as 25MHz Mode.
Alternatively, the device may be operated in 50MHz mode. In this mode, the KSZ8081RNB /
KSZ8091RNB receive the 50 MHz Reference Clock as an input on the XI pin, from pin 12 of the
MII connector J2. This clock may be sourced either from the MAC device, or from a separate
clock source on the MAC board. The following board changes are required to support 50MHz
mode:
1. Remove crystal circuit (Y1, C16, C17) and TXC clock termination (R6).
2. Populate R14 with 0 Ohm and R19 with 33 Ohm to connect RMII 50 MHz reference clock
(from J2 pin 12) to U1 pin 9 (XI input).
Additionally, register 1Fh bit [7] must be set to ‘1’ to select 50MHz mode.
KSZ8081RNB / KSZ8091RNB 10Base-T/100Base-TX Evaluation Board User’s Guide
Micrel, Inc. August 15, 2012
Rev. 1.0
8/13
The MII Management Interface (MIIM) is conducted thru pins MDC (clock line) and MDIO (data
line) on the MII connector J2. MIIM allows upper-layer devices to monitor and control the states of
the KSZ8081RNB / KSZ8091RNB. An external device with MDC/MDIO capability can be used to
read the PHY status or configure the PHY registers. The MIIM frame format and timing
information can be found in the KSZ8081RNB and KSZ8091RNB datasheets and in Clause 22 of
the IEEE 802.3 Specification.
The Eval Board has a 40-pin male edge connector that interfaces with and plugs directly into a
Fast Ethernet MAC board with the mating AMP 787170-4 (40-pin, right angle, female) connector.
Table 1 lists the pin outs for the RMII interface on connector J2.
Pin # Signal Pin # Signal
1 +5V 21 +5V
2 MDIO 22 Ground
3 MDC 23 Ground
4 <not used> 24 Ground
5 <not used> 25 Ground
6 RXD[1] 26 Ground
7 RXD[0] 27 Ground
8 CRSDV 28 Ground
9 <not used> 29 Ground
10 RXER 30 Ground
11 <not used> 31 Ground
12 TXCLK 32 Ground
13 TXEN 33 Ground
14 TXD0 34 Ground
15 TXD1 35 Ground
16 <not used> 36 Ground
17 <not used> 37 Ground
18 <not used> 38 Ground
19 <not used> 39 Ground
20 +5V 40 +5V
Table 1. Connector J2 - RMII Pin Definition
KSZ8081RNB / KSZ8091RNB 10Base-T/100Base-TX Evaluation Board User’s Guide
Micrel, Inc. August 15, 2012
Rev. 1.0
9/13
4.2 Jumper Setting & Definition
At power-up, the KSZ8081RNB / KSZ8091RNB are configured using the chip’s internal pull-up
and pull-down resistors with its default strapping pin values. Jumpers are provided to override the
default settings, allowing for quick configuration and re-configuration of the board. To override the
default settings, simply select and close the desired jumper setting(s) and toggle the on-board
manual reset button (S1) for the new setting(s) to take effect. The KSZ8081RNB-EVAL /
KSZ8091RNB-EVAL strapping jumper settings are defined in Table 2 below.
Jumper Definition Open (default) Close
J3 PHYAD0 1 0
J4 PHYAD1 0 1
J5 PHYAD2 0 1
J6 CONFIG0
CONFIG[2:0] Mode
[open, open, close] RMII
[close, open, close] RMII Back-to-Back
All other CONFIG[2:0] settings not listed are
reserved (not used).
J7 CONFIG1
J8 CONFIG2
J9 Isolate Mode Disable Enable
J10 Nway Auto-Negotiation Enable Disable
J11 Forced Speed (KSZ8081 only) 100Base-TX 10Base-T
J12 Forced Duplex Half Full
J25 Broadcast Off – for PHY Address 0 Broadcast PHY address Unique PHY address
J26 PME_N Pin Enable (KSZ8091 only) Disable Enable
Table 2. KSZ8081RNB-EVAL / KSZ8091RNB-EVAL Strapping Jumper Definition
The KSZ8081RNB-EVAL / KSZ8091RNB-EVAL has another set of jumpers that may be used to
loopback the RMII interface. To loopback, four jumpers must be installed. The individual jumpers
are defined in Table 3.
Jumper RMII Signals Normal Operation RMII Loopback Mode
J13 RXDV / TXEN Open Close
J14 RXC / TXC Open
Close
J16 Not used
J17 RXD1 / TXD1
Open Close
J18 RXD0 / TXD0
Open Close
J19 Not used
Table 3. KSZ8081RNB-EVAL / KSZ8091RNB-EVAL Loopback Jumper Definition
P1-P3P4-P6P7-P9P10-P12P13-P13

KSZ8091RNB-EVAL

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Buy KSZ8091RNB-EVAL
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Description:
Ethernet Development Tools Eval - 10/100 PHY w/EEE & WOL, 0.11u
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New from this manufacturer.
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