REV. A
AD7716
–6–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Inputs to AGND . . . . . . AV
SS
– 0.3 V to AV
DD
+ 0.3 V
V
REF
to AGND . . . . . . . . . . . .AV
SS
– 0.3 V to AV
DD
+ 0.3 V
Digital Inputs to DGND
2
. . . . . . . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to DV
DD
+ 0.3 V
Operating Temperature Range
Commercial Plastic (B Versions) . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
PQFP Package, Power Dissipation . . . . . . . . . . . . . . .450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 95°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 500 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PQFP PINOUT
PLCC PINOUT
NC = NO CONNECT
MODE
NC
D
IN
1
NC
CASCIN
NC
DV
DD
NC
NC
NC
RFS
SCLK
D
OUT
1
DGND
NC
CLKIN
D
OUT
2
DGND
NC
A2
AGND
A
IN
3
AGND
AGND
A
IN
2
CLKOUT
SDATA
NC
AGND
A
IN
4
A0
A1
NC
V
REF
AV
SS
AGND
CASCOUT
AGND
AV
DD
A
IN
1
RESET
4412645
21 24
23
2218
20
19
39
38
35
34
33
37
36
3
7
8
11
12
13
9
10
404142
25 28
27
26
43
31
30
29
32
15
16
17
14
TOP VIEW
(Not to Scale)
AD7716
A2
AGND
TFS
DRDY
26 CASCOUT
NC = NO CONNECT
AGND 12
A2 13
AGND 14
A
IN
2 15
AGND 16
A
IN
3 17
AGND 18
A1 19
AGND 20
A
IN
4 21
A0 22
44 NC
43 CLKIN
42 NC
41 CLKOUT
40 D
OUT
2
38 DGND
37 NC
35 SDATA
34 NC
33 MODE
32 NC
31 NC
30 DV
DD
29 D
IN
1
28 NC
27 CASCIN
25 V
REF
24 AV
SS
23 AGND
NC 1
NC 2
D
OUT
1 3
DGND 4
NC 5
SCLK 7
RESET 8
AGND 9
AV
DD
10
A
IN
1 11
AD7716
TOP VIEW
(Not to Scale)
RFS 6
36 DRDY
39 TFS
ORDERING GUIDE
Temperature Output Noise Package
Model Range (Filter: 146 Hz) Option
*
AD7716BP –40°C to +85°C 11 µV rms P-44A
AD7716BS –40°C to +85°C 11 µV rms S-44
*P = PLCC (Plastic Leaded Chip Carrier); S = PQFP (Plastic Quad Flatpack).
REV. A
–7–
AD7716
PIN DESCRIPTION
Pin Description
AV
DD
Analog Positive Supply, +5 V Nominal. This supplies +ve power to the analog modulators. AV
DD
& DV
DD
must be tied together externally.
DV
DD
Digital Positive Supply, +5 V Nominal. This supplies +ve power to the digital filter and input/output registers.
AV
SS
Analog Negative Supply, –5 V nominal. This supplies –ve power to the analog modulators.
RESET A high pulse on this input pin synchronizes the sampling point on the four input channels. It can be used in a
multichannel system to ensure simultaneous sampling. This also resets the digital interface to a known state.
A0–A2 The three address input pins, A0, A1 and A2 give the device a unique address. This information is contained in
the output data stream from the device.
CLKIN Clock Input for External Clock.
CLKOUT Clock Output which is used to generate an internal master clock by connecting a crystal between CLKOUT and
CLKIN. If an external clock is used then CLKOUT is not connected.
MODE This digital input determines the device interface mode. If it is hardwired low, then the Master Mode interface is
enabled whereas if it is high, the Slave Mode interface is enabled.
CASCIN This is an active-high, level-triggered digital input which is used to enable the output data stream. This input
may be used to cascade several devices in a multichannel system.
CASCOUT Digital output which goes high at the end of a complete 4-channel data transfer. This can be connected to the
CASCIN of the next device in a multichannel system to ensure proper control of the data transfer.
RFS Receive Frame Synchronization signal for the serial output data stream. This can be an input or output depending
on the interface mode.
SDATA Serial Data Input/Output Pin.
SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, depending on the state of the
Mode pin.
DRDY Data Ready Output. A falling edge indicates that a new word is available for transmission. It will return high
when 4, 32-bit words have been transmitted. It also goes high for one clock cycle, when a new word is being
loaded into the output register. Data should not be read during this period.
TFS Transmit Frame Sync input for programming the on-chip Control Register.
D
IN
1 Digital Data Input. This is contained in the digital data stream sent from the device.
D
OUT
1, D
OUT
2 Digital Outputs. These two digital outputs can be programmed from the on-chip Control Register. They can
be used to control calibration signals at the front end.
V
REF
Reference Input, Nominally 2.5 V.
AGND Analog Ground. Ground reference for analog circuitry.
DGND Digital Ground. Ground return for digital circuitry.
A
IN
1–A
IN
4 Analog Input Pins. The analog input range is ±2.5 V.
REV. A
AD7716
–8–
OUTPUT UPDATE RATE
This is the rate at which the digital filter updates the output shift
register. It is a function of the master clock frequency and the
programmed filter cutoff frequency.
FILTER CUTOFF FREQUENCY
The digital filter of the AD7716 can be programmed, in binary
steps, to 5 discrete cutoff frequencies, ranging from 584 Hz to
36.5 Hz (for a CLKIN frequency of 8 MHz).
SETTLING TIME
This is the settling time of the on-chip digital filter, to 0.0007%
of FSR, in response to a full-scale step at the input of the ADC.
It is proportional to the master clock frequency and the filter
cutoff frequency.
USABLE DYNAMIC RANGE
The usable dynamic range is the ratio of the rms full-scale
reading (sine wave input) to the rms noise of the converter,
expressed in dBs. It determines the level to which it is possible
to resolve the input signal. For example, at a bandwidth of
146 Hz, the rms noise of the converter is 11 µV. The full-scale
rms is 1.77 volts. So, the usable dynamic range is 104 dB. Any
signal below this level will be indistinguishable from noise unless
extra post-filtering techniques are employed.
TOTAL HARMONIC DISTORTION
Total harmonic distortion (THD) is the ratio of the rms sum
of the harmonics to the fundamental. For the AD7716, it is
defined as:
THD (dB) = 20 log
V
2
2
+V
3
2
+V
4
2
+V
5
2
+V
6
2
V
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
and V
6
are the rms amplitudes of the second through
sixth harmonics.
ABSOLUTE GROUP DELAY
Absolute group delay is the rate of change of phase versus fre-
quency, dφ/df and is expressed in seconds. For the AD7716,
it is dependent on master clock frequency and filter cutoff
frequency.
DIFFERENTIAL GROUP DELAY
Differential group delay is the total variation in absolute group
delay in the specified bandwidth. Since the digital filter in the
AD7716 has perfectly linear phase, the differential group delay
is almost zero. This is important in many signal processing ap-
plications where excessive differential group delay can cause
phase distortion.
TERMINOLOGY
LINEARITY ERROR
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with Bipolar Zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full scale, a point
0.5 LSB above the last code transition (111 . . . 110 to
111 . . . 111). The error is expressed as a percentage of full
scale.
DIFFERENTIAL LINEARITY ERROR/NO MISSED CODES
This is the difference between any code’s actual width and the
ideal (1 LSB) width. Differential Linearity Error is expressed in
LSBs. A differential linearity specification of ±1 LSB or less
guarantees no missed codes to the full resolution of the device.
The AD7716 has no missed codes guaranteed to 21 bits with a
cutoff frequency of 146 Hz.
GAIN ERROR
Gain Error is the deviation of the last code transition
(111 . . . 110 to 111 . . . 1) from the ideal (V
REF
–3/2 LSBs). It
is expressed as a percentage of full scale.
GAIN TC
This is the variation of gain error with temperature and is ex-
pressed in µV/°C.
OFFSET ERROR
Offset Error is the deviation of the first code transition from the
ideal (–V
REF
+ 0.5 LSB). It is expressed as a percentage of full
scale.
OFFSET TC
This is the variation of offset error with temperature and is ex-
pressed in µV/°C.
NOISE
This is the converter rms noise expressed in µV. Because of the
digital filtering in the sigma delta converter, the noise perfor-
mance is a function of the programmed filter cutoff.
SAMPLING RATE
This is the modulator sampling rate. For the AD7716, it is
f
CLKIN
/14.

AD7716BPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized CMOS 4Ch 22-Bit Data Acquisition System
Lifecycle:
New from this manufacturer.
Delivery:
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