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MK50DX256CMC10

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Introduction
This report applies to mask 5N22D for these products:
• KINETIS
Errata ID Errata Title
6804 CJTAG: Performing a mode change from Standard Protocol to Advanced Protocol may reset the CJTAG.
6990 CJTAG: possible incorrect TAP state machine advance during Check Packet
6939 Core: Interrupted loads to SP can cause erroneous behavior
4588 DMAMUX: When using PIT with "always enabled" request, DMA request does not deassert correctly
6358 ENET: Write to Transmit Descriptor Active Register (ENET_TDAR) is ignored
4710 FTM: FTMx_PWMLOAD register does not support 8-/16-bit accesses
6484 FTM: The process of clearing the FTMx_SC[TOF] bit does not work as expected under a certain condition
when the FTM counter reaches FTM_MOD value.
5641 FlexCAN: Module does not transmit a message that is enabled to be transmitted at a specific moment
during the arbitration process.
6573 JTAG: JTAG TDO function on the PTA2 disables the pull resistor
4590 MCG: Transitioning from VLPS to VLPR low power modes while in BLPI clock mode is not supported.
5130 SAI: Under certain conditions, the CPU cannot reenter STOP mode via an asynchronous interrupt
wakeup event
3981 SDHC: ADMA fails when data length in the last descriptor is less or equal to 4 bytes
3982 SDHC: ADMA transfer error when the block size is not a multiple of four
4624 SDHC: AutoCMD12 and R1b polling problem
3977 SDHC: Does not support Infinite Block Transfer Mode
4627 SDHC: Erroneous CMD CRC error and CMD Index error may occur on sending new CMD during data
transfer
3980 SDHC: Glitch is generated on card clock with software reset or clock divider change
6934 SDHC: Issues with card removal/insertion detection
3983 SDHC: Problem when ADMA2 last descriptor is LINK or NOP
Table continues on the next page...
Freescale Semiconductor
KINETIS_5N22D
Mask Set Errata
Rev 19 DEC 2013
Mask Set Errata for Mask 5N22D
© 2013 Freescale Semiconductor, Inc.
Errata ID Errata Title
3978 SDHC: Software can not clear DMA interrupt status bit after read operation
3984 SDHC: eSDHC misses SDIO interrupt when CINT is disabled
4218 SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the FlexBus is not being used.
5952 SMC: Wakeup via the LLWU from LLS/VLLS to RUN to VLPR incorrectly triggers an immediate wakeup
from the next low power mode entry
3927 TSI: TSI will scan continuously if only one electrode is enabled
3926 TSI: The TSI will run several scan cycles during reference clock instead of scanning each electrode once
2638 TSI: The counter registers are not immediately updated after the EOSF bit is set.
4546 TSI: The counter values reported from TSI increase when in low power modes (LLS, VLLS1, VLLS2,
VLLS3)
4935 UART: CEA709.1 features not supported
7027 UART: During ISO-7816 T=0 initial character detection invalid initial characters are stored in the RxFIFO
7028 UART: During ISO-7816 initial character detection the parity, framing, and noise error flags can set
6472 UART: ETU compensation needed for ISO-7816 wait time (WT) and block wait time (BWT)
4647 UART: Flow control timing issue can result in loss of characters if FIFO is not enabled
4945 UART: ISO-7816 T=1 mode receive data format with a single stop bit is not supported
3892 UART: ISO-7816 automatic initial character detect feature not working correctly
7029 UART: In ISO-7816 T=1 mode, CWT interrupts assert at both character and block boundaries
7090 UART: In ISO-7816 mode, timer interrupts flags do not clear
7031 UART: In single wire receive mode UART will attempt to transmit if data is written to UART_D
5704 UART: TC bit in UARTx_S1 register is set before the last character is sent out in ISO7816 T=0 mode
7091 UART: UART_S1[NF] and UART_S1[PE] can set erroneously while UART_S1[FE] is set
7092 UART: UART_S1[TC] is not cleared by queuing a preamble or break character
5928 USBOTG: USBx_USBTRC0[USBRESET] bit does not operate as expected in all cases
6933 eDMA: Possible misbehavior of a preempted channel when using continuous link mode
e6804: CJTAG: Performing a mode change from Standard Protocol to Advanced
Protocol may reset the CJTAG.
Errata type: Errata
Description: In extremely rare conditions, when performing a mode change from Standard Protocol to
Advanced Protocol on trhe IEEE 1149.7 (Compact JTAG interface) , the CJTAG may reset
itself. In this case, all internal CJTAG registers will be reset and the CJTAG will return to the
Standard Protocol mode.
Workaround: If the CJTAG resets itself while attempting to change modes from Standard Protocol to
Advanced Protocol and Advanced Protocol cannot be enabled after several attempts, perform
future accesses in Standard Protocol mode and do not use the Advanced Protocol feature.
e6990: CJTAG: possible incorrect TAP state machine advance during Check Packet
Errata type: Errata
Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013
2 Freescale Semiconductor, Inc.
Description: While processing a Check Packet, the IEEE 1149.7 module (CJTAG) internally gates the TCK
clock to the CJTAG Test Access Port (TAP) controller in order to hold the TAP controller in the
Run-Test-Idle state until the Check Packet completes. A glitch on the internally gated TCK
could occur during the transition from the Preamble element to the first Body element of Check
Packet processing that would cause the CJTAG TAP controller to change states instead of
remaining held in Run-Test-Idle
If the CJTAG TAP controller changes states during the Check Packet due to the clock glitch,
the CJTAG will lose synchronization with the external tool, preventing further communication.
Workaround: To prevent the possible loss of JTAG synchronization, when processing a Check Packet,
provide a logic 0 value on the TMS pin during the Preamble element to avoid a possible glitch
on the internally gated TCK clock.
e6939: Core: Interrupted loads to SP can cause erroneous behavior
Errata type: Errata
Description: ARM Errata 752770: Interrupted loads to SP can cause erroneous behavior
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
Description
If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/
R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the
load instruction being executed an additional time. For all instructions performing an update to
the base register, the base register will be erroneously updated on each execution, resulting in
the stack-pointer being loaded from an incorrect memory location.
The affected instructions that can result in the load transaction being repeated are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
3) LDR SP,[Rn,#imm]
4) LDR SP,[Rn]
5) LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from an incorrect
memory address are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Conditions
1) An LDR is executed, with SP/R13 as the destination
2) The address for the LDR is successfully issued to the memory system
3) An interrupt is taken before the data has been returned and written to the stack-pointer.
Implications
Mask Set Errata for Mask 5N22D, Rev 19 DEC 2013
Freescale Semiconductor, Inc. 3
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MK50DX256CMC10

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ARM Microcontrollers - MCU Kinetis 256K USB LCD
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