MAX4970/MAX4971/MAX4972
Detailed Description
The MAX4970/MAX4971/MAX4972 overvoltage protec-
tion devices feature a low R
ON
internal FET and protect
low-voltage systems against voltage faults up to +28V.
If the input voltage exceeds the overvoltage threshold,
the internal MOSFET is turned off to prevent damage to
the protected components. These devices also drive an
optional external pFET to protect against reverse-polari-
ty input voltages. The 15ms debounce time prevents
false turn-on of the internal nFET during startup.
Device Operation
The MAX4970/MAX4971/MAX4972 have timing logic
that control the turn-on of the internal nFET. The timing
logic controls the turn-on of the charge pump and the
state of the open-drain ACOK output. If V
IN
< V
UVLO
or
if V
IN
> V
OVLO
, the timing logic disables the charge
pump. If V
UVLO
< V
IN
< V
OVLO
, the internal charge
pump is enabled. The charge-pump startup, after a
15ms debounce delay, turns on the internal nFET (see
the
Functional Diagram
). ACOK is high impedance dur-
ing startup until the ACOK 15ms debounce period
expires. At this point, the device is in its on state. At any
time, if V
IN
drops below V
UVLO
or rises above V
OVLO
,
the charge pump is disabled.
Internal nFET
The MAX4970/MAX4971/MAX4972 incorporate an inter-
nal nFET with a 40mΩ (typ) R
ON
. The nFET is internally
driven by a charge pump that generates a 5V voltage
above IN. The internal nFET is equipped with 2.3A (min)
current-limit protection that turns off the nFET within
10µs (typ) during an overcurrent fault condition.
Autoretry
The MAX4970/MAX4971/MAX4972 have an overcurrent
autoretry function that turns on the nFET again after a
15ms (typ) retry time (see Figure 2). The fast turn-off
time and 15ms retry time result in a very low duty cycle
to keep power consumption low. If the faulty load con-
dition is not present, the nFET remains on.
GP gate Drive
The GP gate drive is controlled by internal logic and by
the EN input. When EN is high, the internal pullup
between GP and IN is active, thus disabling the exter-
nal pFET, and the load is protected against negative
voltages down to the voltage rating of the external
pFET. When EN is active (low), and the input voltage at
IN is above the UVLO threshold, the pulldown between
GP and IN is active, thus enabling the external pFET.
Overvoltage-Protection Controllers
with a Low R
ON
Internal FET
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