AMIS−49587
www.onsemi.com
21
6 bit @ 300 baud
t
10 ms
V
MAINS
ZeroCross
t
ZCD
VIR
M50HZIN
CHIP _CLK
PLL in lock
Start of Physical PreFrame*
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = t
ZCD
to compensate for the zero cross delay
Figure 14. Zero Cross Adjustment to Compensate for Zero Cross Delay (Example for 50 Hz)
The phase difference between the zero crossing of the
mains and CHIP_CLK can be tuned. This opens the
possibility to compensate for external delay t
ZCD
(e.g. opto
coupler) and for the 1.9 V positive threshold VIR
M50HZIN
of
the zero crossing detector. This is done by pre−loading the
PLL counter with a number value stored in register
R_ZC_ADJUST[7:0]. The adjustment period or granularity
is 26 ms. The maximum adjustment is 255 x 26 ms = 6.6 ms
which corresponds with 1/3rd of the mains sine period.
Table 23. ZERO CROSS DELAY COMPENSATION
R_ZC_ADJUST[7:0] Compensation
0000 0000
0 ms
0000 0001
26 ms
0000 0010
52 ms
0000 0011
78 ms
… …
1111 1101
6589 ms
1111 1110
6615 ms
1111 1111
6641 ms
6.1.3 Oscillator
The oscillator works with a standard parallel resonance
crystal of 24 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.
XTAL _IN XTAL _ OUT
C
X
V
SSA
C
X
R
X
24 MHz
Figure 15. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
For correct functionality the external circuit illustrated in
Figure 15 must be connected to the oscillator pins. For a
crystal requiring a parallel capacitance of 20 pF C
X
must be
around 30 pF. (Values of capacitors are indicative only and
are given by the crystal manufacturer). To guarantee startup
the series loss resistance of the crystal must be smaller than
80 W. A parallel resistor R
X
= 1 MW is recommended to
improve the clock symmetry.
The oscillator output f
CLK
= 24 MHz is the base frequency
for the complete IC. The clock frequency for the ARM f
ARM
= f
CLK.
The clock for the transmitter, f
TX_CLK
is equal to
f
CLK
/ 2 or 12 MHz. All the transmitter internal clock signals
will be derived from f
TX_CLK
. The clock for the receiver,
f
RX_CLK
is equal to f
CLK
/ 4 or 6 MHz. All the receiver
internal clock signals will be derived from f
RX_CLK
.
