AMIS−49587
www.onsemi.com
27
Table 26. VALUE OF THE RESISTORS AND
CAPACITORS
Component Value Unit
C
1
1.5 nF
C
2
1.5 nF
C
DREF
1
mF
R
1
22
kW
R
2
11
kW
Remark: The analog part of AMIS−49587 is referenced to
the internal analog ground REF_OUT = 1.65 V (typical
value). If the external circuitry works with a different
analogue reference level one must be sure to place a
decoupling capacitor.
6.3.3 Auto Gain Control (AGC)
The receiver path has a gain stage which is used for
automatic gain control. The gain can be changed in 8 steps
of 6 dB. The control of the AGC is done by a digital circuit
which measures the signal level after the AD converter, and
regulates the average signal in a window around a
percentage of the full scale. The AGC works in 2 cycles: a
measurement cycle at the rising edge of the CHIP_CLK and
an update cycle starting at the next CHIP_CLK.
6.3.4 Low Noise Anti Aliasing Filter
The receiver has a 3rd order continuous time low pass
filter in the signal path. This filter is in fact the same block
as in the transmit path which can be shared because
AMIS−49587 works in half duplex mode. It has a circuit
which tunes the RC time constants of the filter towards the
process characteristics. The C values for the LPF filter are
controlled by the ARM micro controller. When switching
between receive and transmit mode (and visa versa) the tune
circuit does not need to be updated.
6.3.5 A/D Converter
The output of the low pass filter is input for an analog 4th
order sigma−delta converter. The DAC reference levels are
supplied from the reference block. The digital output of the
converter is fed into a noise shaping circuit blocking the
quantization noise from the band of interest, followed by a
sinc5 decimation and a compensation step.
6.3.6 Quadrature Demodulator
The quadrature demodulation block takes the AD signal
and mixes it with the in−phase and quadrature phase of the
f
S
and f
M
carrier frequencies. After a low pass filter and
rectification the mixer output signals are further processed
in software. There the accumulation over a period of
CHIP_CLK is done which results in the discrimination of
data 0 and data 1.
6.4 COMMUNICATION CONTROLLER
The Communication Controller block includes the ARM
32 bit RISC processor operating in the 16−bit Thumb mode,
its peripherals: Data RAM, Program ROM, TIMERS 1 & 2,
Interrupt Control, TEST Control, Watchdog & Power On
Reset (POR), I/O ports and the Serial Communication
Interface (SCI). The micro−processor is programmed to
handle the physical layer (chip synchronization), and the
MAC layer conform to IEC 61334−5−1. The program is
stored in a masked ROM. The RAM contains the necessary
space to store the working data. The back−end interface is
done through the Local Port and Serial Communication
Interface block. This back−end is used for data transmission
with the application micro controller (containing the
application layer for concentrator, power meter, or other
functions) and for the definition of the modem
configuration.
