2
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In the electrical configuration, an automatic power control
(APC) test circuit is included to emulate a semiconductor
laser with a monitor photodiode. Monitor diode current is
provided by transistor Q1, which is controlled by an
operational amplifier (U2). The APC test circuit,
consisting of U2 and Q1, applies the simulated monitor
diode current to the MD pin of the MAX3740. To ensure
proper operation in the electrical configuration, set up the
evaluation board as follows:
1) Place shunts on JU4 - JU8 and JU10 (see the
Adjustment and Control Description
section for
details).
2) Remove shunts JU1 and JU2.
3) To enable the output connect TX_DISABLE to GND
by placing a shunt on JU3.
Note:
When performing the following resistance
checks, autoranging DMMs may forward bias the on-
chip ESD protection and cause inaccurate
measurements. To avoid this, manually set the DMM
to a high range.
4) Adjust R15, the R
BIASSET
potentiometer, for 1.7k
Ω
resistance between TP4 (BIASSET) and ground.
5) Adjust R1, the R
PWRSET
potentiometer, for 10k
Ω
resistance between TP2 (REF) and pin 1 (MD) of
JU2.
6) Adjust R14, the R
PEAKSET
potentiometer, for 20k
Ω
resistance between TP10 (PEAKSET) and ground,
to disable peaking.
7) Adjust R16, the R
TC
potentiometer, for 0
Ω
resistance
between TP7 (TC1) and TP8 (TC2), to disable
temperature compensation.
8) Adjust R2, the R
MODSET
potentiometer, for 10k
Ω
resistance between TP9 (MODSET) and ground.
9) Apply a differential input signal (250mV
P-P
to
2200mV
P-P
) between SMA connectors J5 and J7
(IN+ and IN-).
10) Attach a high-speed oscilloscope with a 50
Ω
input to
SMA connector J6 (OUT).
11) Connect a +3.3V supply between TP20 (V
CC
) and
TP21 (GND). Adjust the power supply until the
voltage between TP11 and ground is +3.3V.
12) Adjust R1 (R
PWRSET
) until desired laser bias current is
achieved.
15) Adjust R14 (R
PEAKSET
) until the desired amount of
peaking is achieved.
For optical evaluation of the MAX3740A, configure the
evaluation kit as follows:
1) Place shunts on JU2, JU6, JU7, JU8 and JU10 (See
the
Adjustment and Control Description
section for
details).
2) Remove components L2 and C9. Remove the shunts
from JU1, JU4 and JU5.
3) Install a 0
Ω
resistor at R7 to connect the anode of
the VCSEL to the output.
4) To enable the output connect TX_DISABLE to GND
by placing a shunt on JU3.
5) Connect a common cathode VCSEL as shown in
Figure 1. Keep leads short to reduce reflection.
Note:
When performing the following resistance
checks, autoranging DMMs may forward bias the on-
chip ESD protection and cause inaccurate
measurements. To avoid this, manually set the DMM
to a high range.
6) Adjust R15, the R
BIASSET
potentiometer, for 1.7k
Ω
resistance between TP4 (BIASSET) and ground.
7) Adjust R1, the R
PWRSET
potentiometer, for 10k
Ω
resistance between TP2 (REF) and pin 1 (MD) of
JU2.
8) Adjust R14, the R
PEAKSET
potentiometer, for 20k
Ω
resistance between TP10 (PEAKSET) and ground,
to disable peaking.
9) Adjust R16, the R
TC
potentiometer, for 0
Ω
resistance
between TP7 (TC1) and TP8 (TC2), to disable
temperature compensation.
