LTC3412A
13
3412afe
ApplicAtions inForMAtion
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
The V
IN
quiescent current loss dominates the efficiency loss
at very low load currents whereas the I
2
R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
1. The V
IN
quiescent current is due to two components: the
DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current
out of V
IN
that is typically larger than the DC bias cur-
rent. In continuous mode, I
GATECHG
= f(QT + QB) where
QT and QB are the gate charges of the internal top and
bottom switches. Both the DC bias and gate charge
losses are proportional to V
IN
; thus, their effects will
be more pronounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I
2
R losses, simply add R
SW
to R
L
and mul-
tiply the result by the square of the average output current.
Other losses including C
IN
and C
OUT
ESR dissipative losses
and inductor core losses generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3412A does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3412A from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum junction
temperature of the part. The temperature rise is given by:
t
r
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 16-lead exposed TSSOP
package, the θ
JA
is 38°C/W. For the 16-lead QFN package
the θ
JA
is 34°C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ t
r
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3412A,
the Exposed Pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
