ISL22329WFU10Z-TK

4
FN6330.2
September 4, 2009
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 3)
MAX
(Note 13) UNIT
I
CC1
V
CC
Supply Current (volatile
write/read)
10k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
1.4 mA
V
CC
Supply Current (volatile
write/read, non-volatile read)
50k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
450 µA
I
CC2
V
CC
Supply Current ( non-volatile
write/read)
10k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
3.5 mA
V
CC
Supply Current (non-volatile
write/read)
50k DCP, f
SCL
= 400kHz; (for I
2
C active,
read and write states)
2.0 mA
I
SB
V
CC
Current (standby) V
CC
= +5.5V , 10k DCP, I
2
C interface in
standby state
1.22 mA
V
CC
= +3.6V, 10k DCP, I
2
C interface in
standby state
800 µA
V
CC
= +5.5V, 50k DCP, I
2
C interface in
standby state
320 µA
V
CC
= +3.6V, 50k DCP, I
2
C interface in
standby state
250 µA
I
SD
V
CC
Current (shutdown) V
CC
= +5.5V @ +85°C, I
2
C interface in
standby state
A
V
CC
= +5.5V @ +125°C, I
2
C interface in
standby state
A
V
CC
= +3.6V @ +85°C, I
2
C interface in
standby state
A
V
CC
= +3.6V @ +125°C, I
2
C interface in
standby state
A
I
LkgDig
Leakage Current, at Pins A0, A1, A2,
SHDN
, SDA, and SCL
Voltage at pin from GND to V
CC
-1 1 µA
t
WRT
(Note 11)
DCP Wiper Response Time SCL falling edge of last bit of DCP data byte
to wiper new position
1.5 µs
t
ShdnRec
(Note 11)
DCP Recall Time From Shutdown
Mode
From rising edge of SHDN
signal to wiper
stored position and RH connection
1.5 µs
SCL falling edge of last bit of ACR data byte
to wiper stored position and RH connection
1.5 µs
Vpor Power-on Recall Voltage Minimum V
CC
at which memory recall
occurs
2.0 2.6 V
VccRamp V
CC
Ramp Rate 0.2 V/ms
t
D
Power-up Delay V
CC
above Vpor, to DCP Initial Value
Register recall completed, and I
2
C Interface
in standby state
3ms
EEPROM SPECIFICATION
EEPROM Endurance 1,000,000 Cycles
EEPROM Retention Temperature T <
+55°C 50 Years
t
WC
(Note 12)
Non-volatile Write Cycle Time 12 20 ms
ISL22329
5
FN6330.2
September 4, 2009
SERIAL INTERFACE SPECS
V
IL
A2, A1, A0, SDA, and SCL Input
Buffer Low Voltage
-0.3 0.3*V
CC
V
V
IH
A2, A1, A0, SDA, and SCL Input
Buffer High Voltage
0.7*V
CC
V
CC
+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis 0.05*
V
CC
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4V
Cpin
(Note 10)
A2, A1, A0, SDA, and SCL Pin
Capacitance
10 pF
f
SCL
SCL Frequency 400 kHz
t
sp
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50 ns
t
AA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
900 ns
t
BUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
CC
crossing 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
CC
crossing 600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
600 ns
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
100 ns
t
HD:DAT
Input Data Hold Time From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
0ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge crossing 70% of V
CC
,
to SDA rising edge crossing 30% of V
CC
600 ns
t
HD:STO
STOP Condition Hold Time for Read,
or Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of V
CC
1300 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window
0ns
t
R
SDA and SCL Rise Time From 30% to 70% of V
CC
20 +
0.1*Cb
250 ns
t
F
SDA and SCL Fall Time From 70% to 30% of V
CC
20 +
0.1*Cb
250 ns
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF
Rpu
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
1kΩ
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 3)
MAX
(Note 13) UNIT
ISL22329
6
FN6330.2
September 4, 2009
SDA vs SCL Timing
A0 and A1 Pin Timing
t
SU:A
A2, A1 and A0 Setup Time Before START condition 600 ns
t
HD:A
A2, A1 and A0 Hold Time After STOP condition 600 ns
NOTES:
3. Typical values are for T
A
= +25°C and 3.3V supply voltage.
4. LSB: [V(R
W
)
127
– V(R
W
)
0
]/127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
5. ZS error = V(RW)
0
/LSB.
6. FS error = [V(RW)
127
– V
CC
]/LSB.
7. DNL = [V(RW)
i
– V(RW)
i-1
]/LSB-1, for i = 1 to 127. i is the DCP register setting.
8. INL = [V(RW)
i
– i • LSB – V(RW)
0
]/LSB for i = 1 to 127.
9. V
MATCH
= [V(RWx)
i
– V(RWy)
i
]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
10. for i = 16 to 112 decimal, T = -40°C to +125°C. Max() is the maximum value of the wiper
voltage and Min () is the minimum value of the wiper voltage over the temperature range.
11. This parameter is not 100% tested.
12. t
WC
is the time from a valid STOP condition at the end of a Write sequence of I
2
C serial interface, to the end of the self-timed internal non-
volatile write cycle.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 3)
MAX
(Note 13) UNIT
TC
V
Max V RW()
i
()Min V RW()
i
()
Max V RW()
i
()Min V RW()
i
()+[]2
----------------------------------------------------------------------------------------------
10
6
+165°C
---------------------
×=
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
t
sp
t
HD:STO
t
HD:A
SCL
SDA
A0, A1
t
SU:A
CLK 1
START
STOP
ISL22329

ISL22329WFU10Z-TK

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DGTL POT 10KOHM 128TAP 10MSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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