AD673JNZ

AD673
REV. A
–3–
ORDERING GUIDE
Temperature Relative
Model Range Accuracy Package Option
1
AD673JN 0°C to +70°C ±1/2 LSB max Plastic DIP (N-20)
AD673JD 0°C to +70°C ±1/2 LSB max Ceramic DIP (D-20)
AD673SD
2
–55°C to +125°C ±1/2 LSB max Ceramic DIP (D-20)
AD673JP 0°C to +70°C ±1/2 LSB max PLCC (P-20A)
NOTES
1
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
2
For details on grade and package offering screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook .
ABSOLUTE MAXIMUM RATINGS
V+ to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
V– to Digital Common . . . . . . . . . . . . . . . . . . . 0 V to –16.5 V
Analog Common to Digital Common . . . . . . . . . . . . . . . ±1 V
Analog Input to Analog Common . . . . . . . . . . . . . . . . . ±15 V
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V+
Digital Outputs (High Impedance State) . . . . . . . . . . 0 V to V+
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
FUNCTIONAL DESCRIPTION
A block diagram of the AD673 is shown in Figure 1. The posi-
tive CONVERT pulse must be at least 500 ns wide.
DR goes
high within 1.5 µs after the leading edge of the convert pulse in-
dicating that the internal logic has been reset. The negative edge
of the CONVERT pulse initiates the conversion. The internal
8-bit current output DAC is sequenced by the integrated injec-
tion logic (I
2
L) successive approximation register (SAR) from its
most significant bit to least significant bit to provide an output
current which accurately balances the input signal current
through the 5 k resistor. The comparator determines whether
the addition of each successively weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is more, the bit is turned off. After testing all bits, the
SAR contains a 8-bit binary code which accurately represents
the input signal to within (0.05% of full scale).
BURIED ZENER REF
COMP-
ARATOR
ANALOG
IN
DB7
V+ V–
DIGITAL
COMMON
CONVERT
INT
CLOCK
8-BIT
SAR
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MSB
LSB
ANALOG
COMMON
BIPOLAR
OFFSET
CONTROL
DATA
READY
AD673
5k
DATA
ENABLE
8-BIT
CURRENT
OUTPUT
DAC
Figure 1. AD673 Functional Block Diagram
The SAR drives DR low to indicate that the conversion is com-
plete and that the data is available to the output buffers.
DATA
ENABLE can then be activated to enable the 8-bits of data de-
sired.
DATA ENABLE should be brought high prior to the next
conversion to place the output buffers in the high impedance state.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset in-
put controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less 1/2 LSB) to
be injected into the summing (+) node of the comparator to off-
set the DAC output. Thus the nominal 0 V to +10 V unipolar
input range becomes a –5 V to +5 V range. The 5 k thin-film
input resistor is trimmed so that with a full-scale input signal, an
input current will be generated which exactly matches the DAC
output with all bits on.
UNIPOLAR CONNECTION
The AD673 contains all the active components required to per-
form a complete A/D conversion. Thus, for many applications,
all that is necessary is connection of the power supplies (+5 V
and –12 V to –15 V), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pinout is shown in Figure 2.
The standard unipolar 0 V to +10 V range is obtained by short-
ing the bipolar offset control pin (Pin 16) to digital common
(Pin 17).
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD673
*
PINS 1 & 2 ARE INTERNALLY
CONNECTED TO TEST POINTS AND SHOULD BE LEFT FLOATING
NC
*
DIGITAL COMMON
DATA READY
NC
DATA ENABLE
NC
*
LSB DB0
DB1
ANALOG IN
ANALOG COMMON
BIPOLAR OFFSET
DB2
DB3
DB4
DB5
DB6
MSB DB7
V+
CONVERT
V–
PIN 1
IDENTIFIER
Figure 2. AD673 Pin Connections
AD673
REV. A
–4–
Full-Scale Calibration
The 5 k thin-film input resistor is laser trimmed to produce a
current which matches the full-scale current of the internal
DAC-plus about 0.3%—when an analog input voltage of 9.961
volts (10 volts – 1 LSB) is applied at the input. The input resis-
tor is trimmed in this way so that if a fine trimming potentio-
meter is inserted in series with the input signal, the input
current at the full scale input voltage can be trimmed down to
match the DAC full-scale current as precisely as desired. How-
ever, for many applications the nominal 9.961 volt full scale can
be achieved to sufficient accuracy by simply inserting a 15 re-
sistor in series with the analog input to Pin 14. Typical full-scale
calibration error will then be within ±2 LSB or ±0.8%. If
more precise calibration is desired, a 200 trimmer should be
used instead. Set the analog input at 9.961 volts, and set the
trimmer so that the output code is just at the transition between
111111 10 and 11111111. Each LSB will then have a weight of
39.06 mV. If a nominal full scale of 10.24 volts is desired
(which makes the LSB have a weight of exactly 40.0 mV), a
100 resistor and a 100 trimmer (or a 200 trimmer with
good resolution) should be used. Of course, larger full-scale
ranges can be arranged by using a larger input resistor, but lin-
earity and full-scale temperature coefficient may be compro-
mised if the external resistor becomes a sizeable percentage of
5 k Figure 3 illustrates the connections required for full-scale
calibration.
Figure 3. Standard AD673 Connections
Unipolar Offset Calibration
Since the Unipolar Offset is less than ±1/2 LSB for all versions
of the AD673, most applications will not require trimming. Fig-
ure 4 illustrates two trimming methods which can be used if
greater accuracy is necessary.
Figure 4a shows how the converter zero may be offset to correct
for initial offset and/or input signal offsets. As shown, the circuit
gives approximately symmetrical adjustment in unipolar mode.
Figure 5 shows the nominal transfer curve near zero for an
AD673 in unipolar mode. The code transitions are at the edges
of the nominal bit weights. In some applications it will be prefer-
able to offset the code transitions so that they fall between the
nominal bit weights, as shown in the offset characteristics.
Figure 5. AD673 Transfer Curve—Unipolar Operation
(Approximate Bit Weights Shown for Illustration,
Nominal Bit Weights % 39.06 mV)
This offset can easily be accomplished as shown in Figure 4b. At
balance (after a conversion) approximately 2 mA flows into the
Analog Common terminal. A 10 resistor in series with this
terminal will result in approximately the desired l/2 bit offset of
the transfer characteristics. The nominal 2 mA Analog Common
current is not closely controlled in manufacture. If high accuracy
is required, a 20 potentiometer (connected as a rheostat) can
be used as R1. Additional negative offset range may be obtained
by using larger values of R1. Of course, if the zero transition
point is changed, the full-scale transition point will also move.
Thus, if an offset of 1/2 LSB is introduced, full scale trimming
as described on the previous page should be done with an analog
input of 9.941 volts.
NOTE: During a conversion, transient currents from the Analog
Common terminal will disturb the offset voltage. Capacitive
decoupling should not be used around the offset network. These
transients will settle appropriately during a conversion. Capaci-
tive decoupling will “pump up” and fail to settle resulting in
conversion errors. Power supply decoupling, which returns to
analog signal common, should go to the signal input side of the
resistive offset network.
Figure 4. Unipolar Offset Trimming
Figure 4a.
Figure 4b.
AD673
REV. A
–5–
BIPOLAR CONNECTION
To obtain the bipolar –5 V to +5 V range with an offset binary
output code, the bipolar offset control pin is left open.
A –5.00 volt signal will give a 8-bit code of 00000000; an input
of 0.00 volts results in an output code of 10000000 and +4.961
volts at the input yields the 11111111 code. The nominal trans-
fer curve is shown in Figure 6.
Figure 6. AD673 Transfer Curve—Bipolar Operation
Note that in the bipolar mode, the code transitions are offset
1/4 LSB such that an input voltage of 0 volts –5 mV to +35 mV
yields the code representing zero (10000000). Each output code
is then centered on its nominal input voltage.
Full-Scale Calibration
Full-Scale Calibration is accomplished in the same manner as in
Unipolar operation except the full-scale input voltage is +4.61
volts.
Negative Full-Scale Calibration
The circuit in Figure 4a can also be used in Bipolar operation to
offset the input voltage (nominally –5 V) which results in the
000000 00 code. R2 should be omitted to obtain a symmetrical
range.
The bipolar offset control input is not directly TTL compatible
but a TTL interface for logic control can be constructed as
shown in Figure 7.
Figure 7. Bipolar Offset Controlled by Logic Gate
Gate Output = 1 Unipolar 0 V–10 V Input Range
Gate Output = 0 Bipolar
±
5 V Input Range
SAMPLE-HOLD AMPLIFIER CONNECTION
TO THE AD673
Many situations in high-speed acquisition systems or digitizing
rapidly changing signals require a sample-hold amplifier (SHA)
in front of the A-D converter. The SHA can acquire and hold a
signal faster than the converter can perform a conversion. A
SHA can also be used to accurately define the exact point in
time at which the signal is sampled. For the AD673, a SHA can
also serve as a high input impedance buffer.
Figure 8 shows the AD673 connected to the AD582 monolithic
SHA for high speed signal acquisition. In this configuration, the
AD582 will acquire a 10 volt signal in less than 10 µs with a
droop rate less than 100 µV/ms.
DR goes high after the conversion is initiated to indicate that re-
set of the SAR is complete. In Figure 8 it is also used to put the
AD582 into the hold mode while the AD673 begins its conver-
sion cycle. (The AD582 settles to final value well in advance of
the first comparator decision inside the AD673).
DR goes low when the conversion is complete placing the
AD582 back in the sample mode. Configured as shown in Fig-
ure 8, the next conversion can be initiated after a 10 µs delay to
allow for signal acquisition by the AD582.
Observe carefully the ground, supply, and bypass capacitor con-
nections between the two devices. This will minimize ground
noise and interference during the conversion cycle.
Figure 8. Sample-Hold Interface to the AD673

AD673JNZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 8-bit Successive Approx
Lifecycle:
New from this manufacturer.
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