ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
4
IDT
®
K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10
General Description
The ICS932S805 is a main clock synthesizer chip that, when paired with ICS9DB108, provides all clocks required by
Serverworks HT2100-based servers.
An SMBus interface allows full control of the device.
Block Diagram
I
R
E
F
PCICLK(1:0)
CONTROL
LOGIC
XTAL
OSC.
CPUCLK8(6:0)
FIXED PLL
48MHz(2:0)
R
E
F
(
2
:
0
)
X1
X2
PCI33
DIV
CPU
DIV
S DATA
SCLK
FS(3:0)
SPREAD_EN
SRC
DIV1
SRCCLK(5:0)
PD#
25MHz(1:0)25M
DIV
25MHz PLL
CPU/SRC/
PCI PLL
Zo = 50 ohms Zo = 55 ohms Zo = 60 ohms
48MHz 1 Load 1 15 24 30
48MHz 2 Load 2 4.7 15 20
25MHz 1 Load 1 15 24 30
25MHz 2 Load 2 4.7 15 20
PCI 1 Load 1 15 24 30
PCI 2 Load 2 4.7 15 20
REF 1 Load 1 15 24 30
REF 2 Load 2 4.7 15 20
Number of
Loads on Board
Series Resistor for Pro
p
er Termination
Single-ended Terminations
Single-ended
Out
p
ut Stren
g
th
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
5
IDT
®
K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10
CPU Divider Ratios
Bit00011011MSB
00
0000
4
0100
8
1000
16
1100
32
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
15
0111
30
1011
60
1111
120
LSB
Address Div Address Div Address Div Address Div
PCI Divider Ratios
Bit00011011MSB
00
0000
4
0100
8
1000
16
1100
32
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
15
0111
30
1011
60
1111
120
LSB
Address Div Address Div Address Div Address Div
SRC Divider Ratios
Bit00011011MSB
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB
Address Div Address Div Address Div Address Div
Divider (3:2)
Divider (1:0)
Divider (3:2)
Divider (1:0)
Divider (3:2)
Divider (1:0)
ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
6
IDT
®
K8 Clock Chip for Serverworks HT2100 Servers 1131D – 05/04/10
General SMBus serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Data Byte Count = X
ACK
Slave Address D3
(h)
Index Block Read Operation
Slave Address D2
(h)
Beginning Byte = N
ACK
ACK

932S805CGLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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