19
LT1578/LT1578-2.5
APPLICATIONS INFORMATION
WUU
U
At power-up, when V
C
is being clamped by the FB pin (see
Figure 2, Q2), the sync function is disabled. This allows the
frequency foldback to operate in the shorted output con-
dition. During normal operation, switching frequency is
controlled by the internal oscillator until the FB pin reaches
0.7V, after which the SYNC pin becomes operational. If no
synchronization is required, this pin should be connected
to ground.
THERMAL CALCULATIONS
Power dissipation in the LT1578 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
P
RI V
V
ns I V f
SW
SW OUT OUT
IN
OUT IN
=
()( )
+
()()()
2
60
Boost current loss:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
50/
Quiescent current loss:
PV V
V
V
Q IN OUT
OUT
IN
=
+
+
()
−−
055 10 16 10
0 004
33
2
.• .
.
R
SW
= Switch resistance (0.2)
60ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 1A:
P
W
PW
P
SW
BOOST
Q
=
()()()
+
()( )
=+ =
=
()( )
=
=
+
+
()( )
=
−−
02 1 5
10
60 10 1 10 200 10
01 012 022
5150
10
005
10 0 55 10 5 1 6 10
5 0 004
10
0
2
93
2
33
2
.
••
.. .
/
.
.• .
.
.. 02W
Total power dissipation is 0.22 + 0.05 + 0.02 = 0.29W.
Thermal resistance for LT1578 package is influenced by
the presence of internal or backside planes. With a full
plane under the SO package, thermal resistance will be
about 80°C/W. No plane will increase resistance to about
120°C/W. To calculate die temperature, add in worst-case
ambient temperature:
T
J
= T
A
+ θ
JA
(P
TOT
)
With the SO-8 package (θ
JA
= 80°C/W), at an ambient
temperature of 50°C,
T
J
= 50 + 80 (0.29) = 73.2°C
Die temperature is highest at low input voltage, so use
lowest continuous input operating voltage for thermal
calculations.
FREQUENCY COMPENSATION
Loop frequency compensation of switching regulators
can be a rather complicated problem because the reactive
components used to achieve high efficiency also intro-
duce multiple poles into the feedback loop. The inductor
and output capacitor on a conventional step-down con-
verter actually form a resonant tank circuit that can exhibit
peaking and a rapid 180° phase shift at the resonant
frequency. By contrast, the LT1578 uses a “current mode”
architecture to help alleviate the phase shift created by the
inductor. The basic connections are shown in Figure 9.
Figure 10 shows a Bode plot of the phase and gain of the
power section of the LT1578, measured from the V
C
pin to
20
LT1578/LT1578-2.5
APPLICATIONS INFORMATION
WUU
U
the output. Gain is set by the 1.5A/V transconductance of
the LT1578 power section and the effective complex
impedance from output to ground. Gain rolls off smoothly
above the 160Hz pole frequency set by the 100µF output
capacitor. Phase drop is limited to about 85°. Phase
recovers and gain levels off at the zero frequency (16kHz)
set by capacitor ESR (0.1).
Error amplifier transconductance phase and gain are shown
in Figure 11. The error amplifier can be modeled as a
transconductance of 1000µMho, with an output imped-
ance of 570k in parallel with 2.4pF. In all practical
applications, the compensation network from the V
C
pin to
ground has a much lower impedance than the output
impedance of the amplifier at frequencies above 200Hz.
This means that the error amplifier characteristics them-
selves do not contribute excess phase shift to the loop, and
the phase/gain characteristics of the error amplifier sec-
tion are completely controlled by the external compensa-
tion network.
In Figure 12, full loop phase/gain characteristics are
shown with a compensation capacitor of 100pF, giving the
error amplifier a pole at 2.8kHz, with phase rolling off to
90° and staying there. The overall loop has a gain of 66dB
at low frequency, rolling off to unity-gain at 58kHz. The
phase plot shows a two-pole characteristic until the ESR
of the output capacitor brings it back to single pole above
16kHz. Phase margin is about 77° at unity-gain.
FREQUENCY (Hz)
GAIN (µMho)
PHASE (DEG)
2000
1500
1000
500
0
500
200
150
100
50
0
–50
10 1k 10k 1M
1578 F11
100 100k
GAIN
PHASE
R
OUT
570k
C
OUT
2.4pF
V
C
ERROR AMPLIFIER EQUIVALENT CIRCUIT
R
LOAD
= 50
V
FB
1 × 10
–3
)(
+
1.21V
V
SW
V
C
LT1578
GND
1578 F09
R1
OUTPUT
ESR
C
F
C
C
R
C
ERROR
AMPLIFIER
FB
R2
C1
CURRENT MODE
POWER STAGE
g
m
= 1.5A/V
+
Figure 10. Response from V
C
Pin to Output
FREQUENCY (Hz)
10
GAIN (dB)
PHASE (DEG)
40
20
0
–20
–40
40
0
–40
–80
120
100 1k
1578 F07
10k 100k
GAIN
PHASE
V
IN
= 10V
V
OUT
= 5V
I
OUT
= 500mA
Figure 12. Overall Loop Characteristics
FREQUENCY (Hz)
LOOP GAIN (dB)
LOOP PHASE (DEG)
80
60
40
20
0
–20
180
135
90
45
0
–45
10 1k 10k 1M
1578 F12
100 100k
V
IN
= 10V
V
OUT
= 5V
I
OUT
= 500mA
C
OUT
= 100µF
10V, AVX TPS
C
C
= 100pF
L = 30µH
PHASE
GAIN
Figure 9. Model for Loop Response Figure 11. Error Amplifier Gain and Phase
21
LT1578/LT1578-2.5
APPLICATIONS INFORMATION
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Analog experts will note that around 7kHz, phase dips
close to the zero phase margin line. This is typical of
switching regulators, especially those that operate over a
wide range of loads. This region of low phase is not a
problem as long as it does not occur near unity-gain. In
practice, the variability of output capacitor ESR tends to
dominate all other effects with respect to loop response.
Variations in ESR
will
cause unity-gain to move around,
but at the same time phase moves with it so that adequate
phase margin is maintained over a very wide range of ESR
( ±3:1).
What About a Resistor in the Compensation Network?
It is common practice in switching regulator design to add
a “zero” to the error amplifier compensation to increase
loop phase margin. This zero is created in the external
network in the form of a resistor (R
C
) in series with the
compensation capacitor. Increasing the size of this resis-
tor generally creates better and better loop stability, but
there are two limitations on its value. First, the combina-
tion of output capacitor ESR and a large value for R
C
may
cause loop gain to stop rolling off altogether, creating a
gain margin problem. An approximate formula for R
C
where gain margin falls to zero is:
R Loop
V
G G ESR
C
OUT
MP MA
Gain =1
()
=
()()()()
121.
G
MP
= Transconductance of power stage = 1.5A/V
G
MA
= Error amplifier transconductance = 1(10
–3
)
ESR = Output capacitor ESR
1.21 = Reference voltage
With V
OUT
= 5V and ESR = 0.1, a value of 27.5k for R
C
would yield zero gain margin, so this represents an upper
limit. There is a second limitation however which has
nothing to do with theoretical small signal dynamics. This
resistor sets high frequency gain of the error amplifier,
including the gain at the switching frequency. If the
switching frequency gain is high enough, an excessive
amout of output ripple voltage will appear at the V
C
pin
resulting in improper operation of the regulator. In a
marginal case,
subharmonic
switching occurs, as
evidenced by alternating pulse widths seen at the switch
node. In more severe cases, the regulator squeals or
hisses audibly even though the output voltage is still
roughly correct. None of this will show on a Bode plot
since this is an amplitude insensitive measurement.
Tests
have shown that if ripple voltage on the V
C
is held to less
than 100mV
P-P
, the LT1578 will generally be well behaved
.
The formula below will give an estimate of V
C
ripple
voltage when R
C
is added to the loop, assuming that R
C
is
large compared to the reactance of C
C
at 200kHz.
V
R G V V ESR
VLf
C RIPPLE
C MA IN OUT
IN
()
=
()( )
()()()
()()()
121.
G
MA
= Error amplifier transconductance (1000µMho)
If a series compensation resistor of 15k gave the best
overall loop response, with adequate gain margin, the
resulting V
C
pin ripple voltage with V
IN
= 10V, V
OUT
= 5V,
ESR = 0.1, L = 30µH, would be:
V
k
V
C RIPPLE
()
=
()
()
()()()
()
()()
=
15 1 10 10 5 01 121
10 30 10 200 10
0 151
3
63
•..
••
.
This ripple voltage is high enough to possibly create
subharmonic switching. In most situations a compromise
value (<10k in this case) for the resistor gives acceptable
phase margin and no subharmonic problems. In other
cases, the resistor may have to be larger to get acceptable
phase response, and some means must be used to control
ripple voltage at the V
C
pin. The suggested way to do this
is to add a capacitor (C
F
) in parallel with the R
C
/C
C
network
on the V
C
pin. The pole frequency for this capacitor is
typically set at one-fifth of the switching frequency so that
it provides significant attenuation of the switching ripple,
but does not add unacceptable phase shift at the loop
unity-gain frequency. With R
C
= 15k,
C
fR
k
pF
F
C
=
()()()
=
()
()
=
5
2
5
2 200 10 15
265
3
π
π

LT1578IS8-2.5#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5A, 200kHz Buck Sw Reg
Lifecycle:
New from this manufacturer.
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