1/9September 2002
■ SET RESET CAPABILITY
■ STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINETELY WITH CLOCK LEVEL
EITHER ”HIGH” OR ”LOW”
■ MEDIUM-SPEED OPERATION - 16MHz
(Typ. clock toggle rate at 10V)
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
=25°C
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B ” STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES”
DESCRIPTION
HCF4027B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4027B is a single monolithic chip integrated
circuit containing two identical
complementary-symmetry J-K master-slave
flip-flops. Each flip-flop has provisions for
individual J, K, Set, Reset, and Clock input
signals. Buffered Q and Q signals are provided as
outputs. This input-output arrangement provides
for compatible operation with the HCF4013B dual
D type flip-flop.
This device is useful in performing control,
register, and toggle functions. Logic levels present
at the J and K inputs, along with internal
self-steering, control the state of each flip-flop;
changes in the flip-flop stateare synchronous with
the positive-going transition of the clock pulse. Set
and Reset functions are independent of the clock
and are initiated when a high level signal is
present at either the Set or Reset input.
HCF4027B
DUAL J-K MASTER SLAVE FLIP-FLOP
PIN CONNECTION
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4027BEY
SOP HCF4027BM1 HCF4027M013TR
DIP SOP
