DOC#: SP-AP-0014 (Rev. 0.2) Page 3 of 13
EProClock
®
Programmable Technology
EProClock
®
is the world’s first non-volatile programmable
clock. The EProClock
®
technology allows board designer to
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock
®
technology can be configured through SMBus or
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
Frequency/Spread Select Pin SS[1:0]
Apply the appropriate logic levels to SS [1:0] inputs before
CKPWRGD assertion to achieve clock frequency selection.
When the clock chip sampled HIGH on CKPWRGD and
indicates that the voltage is stable then SS [1:0] input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other
SS[1:0], and CKPWRGD transitions are ignored.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
Frequency/Spread Select Pin (SS[1:0])
SS1 SS0
Frequency
(MHz)
Spread
(%) Note
0 0 100.00 OFF Default Value for SS [1:0] =00
0 1 100.00 - 0.5
1 0 100.00 +/- 0.25
1 1 100.00 - 0.75
MID 0 125 OFF
MID 1 200 OFF
Table 1. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1Start 1Start
