LTC2856-1/LTC2856-2
LTC2857-1/LTC2857-2
LTC2858-1/LTC2858-2
13
285678ff
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applicaTions inFormaTion
High Speed Considerations
A ground plane layout is recommended. A 0.1µF bypass
capacitor less than one-quarter inch away from the V
CC
pin
is also recommended. The PC board traces connected to
signals A/B and Z/Y should be symmetrical and as short
as possible to maintain good differential signal integrity.
To minimize capacitive effects, the differential signals
should be separated by more than the width of a trace
and should not be routed on top of each other if they are
on different signal planes.
Care should be taken to route outputs away from any
sensitive inputs to reduce feedback effects that might
cause noise, jitter or even oscillations. For example, in the
full-duplex LTC2857-1, DI and A/B should not be routed
near the driver or receiver outputs.
The logic inputs have 100mV of hysteresis to provide noise
immunity. Fast edges on the outputs can cause glitches in
the ground and power supplies which are exacerbated by
capacitive loading. If a logic input is held near its threshold
(typically 1.5V), a noise glitch from a driver transition may
exceed the hysteresis levels on the logic and data input
pins causing an unintended state
change. This can be
avoided by
maintaining normal logic levels on the pins
and by slewing inputs through their thresholds by faster
than 1V/µs when transitioning. Good supply decoupling
and proper line termination also reduce glitches caused
by driver transitions.
Cable Length vs Data Rate
For a given data rate, the maximum transmission distance
is bounded by the cable properties. A typical curve of cable
length vs data rate compliant with the RS485 standard is
shown in Figure 9. Three regions of this curve reflect differ
-
ent performance limiting factors in data transmission. In the
flat region of the curve, maximum distance is determined
by resistive losses in the cable. The downward sloping
region represents limits in distance and data rate due to
AC losses in the cable. The solid vertical line represents
the specified maximum data rate in the RS485 standard.
The dashed line at 250kbps shows the maximum data rate
of the low-EMI LTC2856-2, LTC2857-2, and LTC2858-2.
The dashed line at 20Mbps shows the maximum data rates
of the LTC2856-1, LTC2857-1 and LTC2858-1.
Figure 8. Supply Current vs Data Rate
Cable Termination
Proper cable termination is very important for good signal
fidelity. If the cable is
not terminated with
its characteristic
impedance, reflections will result in distorted waveforms.
RS485 transceivers typically communicate over twisted-
pair cables with characteristic impedance ranging from
100Ω to 120Ω. Each end of the network should be termi
-
nated with
a discrete resistor matching the characteristic
impedance or
with an LTC2859/LTC2861 transceiver with
integrated termination capability.
Figure 9. Cable Length vs Data Rate
(RS485 Standard Shown in Solid Vertical Lines)
DATA RATE (kbps)
10
2
45
CURRENT (mA)
65
70
75
10
3
10
4
10
5
285678 F08
60
55
50
R
DIFF
= 54Ω
C
L
= 1000pF
C
L
= 100pF
285678 F09
DATA RATE (bps)
CABLE LENGTH (FT)
10k 1M 10M100k 100M
100
1k
10
10k
LOW-EMI MODE
MAX DATA RATE
RS485 MAX
DATA RATE
NORMAL
MODE MAX
DATA RATE
LTC2856-1/LTC2856-2
LTC2857-1/LTC2857-2
LTC2858-1/LTC2858-2
14
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For more information www.linear.com/LTC2856-1
Failsafe “0” Application (Idle State = Logic “0”)
Typical applicaTions
D
V
CC
I
1
I
2
100k
B
A
“A”
“B”
RO
DI
LTC2856-1
285678 TA02
R
applicaTions inFormaTion
Time-Based Traces Frequency Spectrum
Figure 10. LTC2858-1 Driver Output at 100kHz Into 100Ω Resistor
Figure 11. LTC2858-2 Driver Output at 100kHz Into 100Ω Resistor
2µs/DIV
Y, Z
1V/DIV
Y-Z
2V/DIV
285678 F10a
1.25MHz/DIV
Y-Z
10dB/DIV
285678 F10b
2µs/DIV
Y-Z
2V/DIV
Y, Z
1V/DIV
285678 F11a
1.2MHz/DIV
Y-Z
10dB/DIV
285678 F11b
LTC2856-1/LTC2856-2
LTC2857-1/LTC2857-2
LTC2858-1/LTC2858-2
15
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For more information www.linear.com/LTC2856-1
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 0509 REV C
0.25 ±0.05
2.38 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.65 ±0.05
(2 SIDES)2.10 ±0.05
0.50
BSC
0.70 ±0.05
3.5
±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)

LTC2858IMS-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
RS-422/RS-485 Interface IC 5V Full-Duplex 250kbps RS485 Transceiver w/ Enables
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union