ADG428BPZ-REEL

REV. C
ADG428/ADG429
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, WR, RS, S or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
ORDERING GUIDE
Model
1
Temperature Range Package Options
2
ADG428BN –40°C to +85°C N-18
ADG428BP –40°C to +85°C P-20A
ADG428BR –40°C to +85°C R-18
ADG428TQ –55°C to +125°CQ-18
ADG429BN –40°C to +85°C N-18
ADG429BP –40°C to +85°C P-20A
ADG429TQ –55°C to +125°CQ-18
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
R = Small Outline IC (SOIC).
ADG429 PIN CONFIGURATIONS
DIP/SOIC PLCC
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG428
D
S4
WR
A0
EN
V
SS
S3
S2
S1
S8
S7
RS
A1
A2
GND
S6
S5
V
DD
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1
S2
S3
A2
GND
V
DD
S5
S6
ADG428
A0
WR
NC
RS
A1
S4
D
NC
S8
S7
DIP PLCC
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG429
DA
S4A
WR
A0
EN
V
SS
S3A
S2A
S1A
DB
S4B
RS
A1
GND
V
DD
S3B
S2B
S1B
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1A
S2A
S3A
GND
V
DD
S1B
S2B
S3B
ADG429
A0
WR
NC
RS
A1
S4A
DA
NC
DB
S4B
ADG428 PIN CONFIGURATIONS
REV. C
ADG428/ADG429
–5–
ADG428 Truth Table
A2 A1 A0 EN WR RS ON SWITCH
Latching
XXXX
g
1 Maintains Previous
Switch Condition
Reset
XXXXX0 NONE
(Latches Cleared)
Transparent Operation
X X X 0 0 1 NONE
000101 1
001101 2
010101 3
011101 4
100101 5
101101 6
110101 7
111101 8
ADG429 Truth Table
A1 A0 EN WR RS ON SWITCH PAIR
Latching
XXX
g
1 Maintains Previous
Switch Condition
Reset
XXXX0 NONE
(Latches Cleared)
Transparent Operation
X X 0 0 1 NONE
001011
011012
101013
111014
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
GND Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
R
ON
Difference between the R
ON
of any two
channels.
I
S
(OFF) Source leakage current when the switch is off.
I
D
(OFF) Drain leakage current when the switch is off.
I
D
, I
S
(ON) Channel leakage current when the switch is
on.
V
D
(V
S
) Analog voltage on terminals D, S.
C
S
(OFF) Channel input capacitance for “OFF”
condition.
C
D
(OFF) Channel output capacitance for “OFF”
condition.
C
D
, C
S
(ON) “ON” switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN) Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
t
OFF
(EN) Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
t
TRANSITlON
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
t
OPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for Logic “0.”
V
INH
Minimum input voltage for Logic “1.”
I
INL
(I
INH
) Input current of the digital input.
Crosstalk A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling
through an “OFF” channel.
Charge A measure of the glitch impulse transferred
Injection from the digital input to the analog output
during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
REV. C
ADG428/ADG429
–6–
TIMING DIAGRAMS
3V
WR
0V
3V
A0, A1, (A2)
EN
0V
50% 50%
t
W
t
S t
H
2V
0.8V
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2.
Figure 2 shows the Reset Pulsewidth, t
RS
, and the Reset Turnoff
Time, t
OFF
, (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tr = tf = 20 ns.
Typical Characteristics
V
D
(V
S
) – Volts
140
40
–15 15–10
R
ON
V
–5 0 5 10
130
100
70
80
V
DD
= +15V
V
SS
= –15V
60
50
120
110
90
T
A
= +258C
V
DD
= +5V
V
SS
= –5V
V
DD
= +12V
V
SS
= –12V
V
DD
= +10V
V
SS
= –10V
Figure 3. R
ON
as a Function of V
D
(V
S
): Dual Supply
Voltage
V
D
(V
S
) – Volts
80
40
R
ON
V
75
60
55
50
45
70
65
–15 15–10
–5
0510
V
DD
= +15V
V
SS
= –15V
+1258C
+858C
+258C
Figure 4. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures
V
D
(V
S
) – Volts
600
550
100
01536912
400
250
200
150
500
450
300
350
R
ON
V
50
0
T
A
= +258C
V
DD
= +12V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V
V
DD
= +5V
V
SS
= 0V
V
DD
= +15V
V
SS
= 0V
Figure 5. R
ON
as a Function of V
D
(V
S
): Single Supply
Voltage
V
D
(V
S
) – Volts
160
60
0152
R
ON
V
46810
150
120
90
80
70
140
130
110
100
V
DD
= +12V
V
SS
= 0V
+1258C
+258C
+858C
Figure 6. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures

ADG428BPZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 60 Ohm LC2MOS High Performance
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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