OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74HCT595ADR2G

P1-P3P4-P6P7-P9P10-P11
MC74HCT595A
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
4.5
to
5.5
2.0 2.0 2.0 V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
4.5
to
5.5
0.8 0.8 0.8 V
V
OH
Minimum High−Level Output
Voltage, Q
A
− Q
H
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
4.5 4.4 4.4 4.4
V
V
in
= V
IH
or V
IL
|I
out
| v 6.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage, Q
A
− Q
H
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
4.5 0.1 0.1 0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 6.0 mA 4.5 0.26 0.33 0.4
V
OH
Minimum High−Level Output
Voltage, SQ
H
V
in
= V
IH
or V
IL
II
out
I v 20 mA
4.5 4.4 4.4 4.4
V
V
in
= V
IH
or V
IL
II
out
I
v
4.0 mA 4.5 3.98 3.84 3.7
V
OL
Maximum Low−Level Output
Voltage, SQ
H
V
in
= V
IH
or V
IL
II
out
I v 20 mA
4.5 0.1 0.1 0.1
V
V
in
= V
IH
or V
IL
II
out
I
v
4.0 mA 4.5 0.26 0.33 0.4
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 5.5 ± 0.1 ± 1.0 ± 1.0
mA
I
OZ
Maximum Three−State
Leakage
Current, Q
A
− Q
H
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.5 ± 5.0 ± 10
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
l
out
= 0 mA
5.5 4.0 40 160
mA
DI
CC
Additional Quiescent Supply
Current
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
5.5
≥ −55°C 25 to 125°C
mA
2.9 2.4
MC74HCT595A
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_ C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
4.5 to
5.5
30 24 20 MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1 and 7)
4.5 to
5.5
28 35 42 ns
t
PHL
Maximum Propagation Delay, Reset to SQ
H
(Figures 2 and 7)
4.5 to
5.5
29 36 44 ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Clock to Q
A
− Q
H
(Figures 3 and 7)
4.5 to
5.5
28 35 42 ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
A
− Q
H
(Figures 4 and 8)
4.5 to
5.5
30 38 45 ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
A
− Q
H
(Figures 4 and 8)
4.5 to
5.5
27 34 41 ns
t
TLH
,
t
THL
Maximum Output Transition Time, Q
A
− Q
H
(Figures 3 and 7)
4.5 to
5.5
12 15 18 ns
t
TLH
,
t
THL
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
4.5 to
5.5
15 19 22 ns
C
in
Maximum Input Capacitance — 10 10 10 pF
C
out
Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q
A
− Q
H
— 15 15 15 pF
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
300
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
TIMING REQUIREMENTS (Input t
r
= t
f
= 6.0 ns)
Symbol Parameter
V
CC
V
Guaranteed Limit
Unit
25_C to –55_C v 85_C v 125_C
t
su
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
4.5 to
5.5
10 13 15 ns
t
su
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
4.5 to
5.5
15 19 22 ns
t
h
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
4.5 to
5.5
5.0 5.0 5.0 ns
t
rec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
4.5 to
5.5
10 13 15 ns
t
w
Minimum Pulse Width, Reset
(Figure 2)
4.5 to
5.5
12 15 18 ns
t
w
Minimum Pulse Width, Shift Clock
(Figure 1)
4.5 to
5.5
10 13 15 ns
t
w
Minimum Pulse Width, Latch Clock
(Figure 6)
4.5 to
5.5
10 13 15 ns
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
4.5 to
5.5
500 500 500 ns
MC74HCT595A
http://onsemi.com
6
FUNCTION TABLE
Operation
Inputs Resulting Function
Reset
Serial
Input
A
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
Serial
Output
SQ
H
Parallel
Outputs
Q
A
− Q
H
Reset shift register L X X L, H, ↓ L L U L U
Shift data into shift
register
H D ↑ L, H, ↓ L D → SR
A
;
SR
N
→ SR
N+1
U SR
G
→ SR
H
U
Shift register remains
unchanged
H X L, H, ↓ L, H, ↓ L U U U U
Transfer shift register
contents to latch
register
H X L, H, ↓ ↑ L U SR
N
→ LR
N
U SR
N
Latch register remains
unchanged
X X X L, H, ↓ L * U * U
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into high
impedance state
X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level ↑ = Low−to−High * = depends on Reset and Shift Clock inputs
LR = latch register contents U = remains unchanged ↓ = High−to−Low ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
Shift Register Clock Input. A low− to−high transition on
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
Active−low, Asynchronous, Shift Register Reset Input. A
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A low−to−high transition on
this input latches the shift register data.
Output Enable (Pin 13)
Active−low Output Enable. A low on this input allows the
data from the latches to be presented at the outputs. A high
on this input forces the outputs (Q
A
−Q
H
) into the
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
Q
A
− Q
H
(Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3−state, latch outputs.
SQ
H
(Pin 9)
Noninverted, Serial Data Output. This is the output of the
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
P1-P3P4-P6P7-P9P10-P11

MC74HCT595ADR2G

Mfr. #:
Buy MC74HCT595ADR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers IC SHIFT REGISTER 8BIT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet