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87021AMILF

P1-P3P4-P6P7-P9P10-P12P13-P14
÷1/÷2 Differential-to-LVCMOS/LVTTL
Clock Generator
87021I
Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 25, 20161
GENERAL DESCRIPTION
The 87021I is a high performance ÷1/÷2 Differential-to-LVCMOS/
LVTTL Clock Generator and a member of the family of High
Performance Clock Solutions from IDT. The CLK, nCLK pair can
accept most standard differential input levels. Guaranteed part-
to-part skew characteristics make the 87021I ideal for those clock
distribution applications demanding well defi ned performance
and repeatability.
FEATURES
• Two single-ended LVCMOS/LVTTL outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Additive phase jitter, RMS: 0.18ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Propagation delay: 3.4ns (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Availalbe in lead-free (RoHS 6) package
BLOCK DIAGRAM PIN ASSIGNMENT
87021I
8-Lead SOIC
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
CLK
nCLK
MR
F_SEL
1
2
3
4
VDD
Q0
Q1
GND
8
7
6
5
Q0
Q1
CLK
nCLK
MR
F_SEL
0
1
÷1
÷2
R
87021I Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 25, 20162
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance
(per output)
V
DD
= 3.465V 24 pF
V
DD
= 2.625V 16 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
OUT
Output Impedance V
DD
= 3.465V 9
Ω
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal divid-
ers and the outputs are enabled. LVCMOS / LVTTL interface levels. See
Table 3.
4 F_SEL Input Pulldown
Selects divider value for Qx outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
5 GND Power Power supply ground.
6 Q1 Output Singled-ended output. LVCMOS/LVTTL interface levels.
7 Q0 Output Singled-ended output. LVCMOS/LVTTL interface levels.
8V
DD
Power Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87021I Data Sheet
©2016 Integrated Device Technology, Inc Revision B January 25, 20163
TABLE 3. FUNCTION TABLE
FIGURE 1. TIMING DIAGRAM
MR F_SEL Divide Value
1 X Reset: Q0, Q1 outputs low
00 ÷1
01 ÷2
CLOCK
CLOCK
MR
÷1
MR
÷2
P1-P3P4-P6P7-P9P10-P12P13-P14

87021AMILF

Mfr. #:
Buy 87021AMILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PLL Based Clock Generator
Lifecycle:
New from this manufacturer.
Delivery:
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