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SI9145BQ-T1-E3

P1-P3P4-P6P7-P9P10-P12P13-P14
Si9145
Vishay Siliconix
Document Number: 70021
S-40710—Rev. K, 19-Apr-04
www.vishay.com
7
TIMING WAVEFORMS
ENABLE
MODE SELECT
UVLO
SET
R
OSC
C
OSC
OUTPUT
D
MAX
/SS
1.2 V
1.0 V
ON
OFF
>1.5 V
Set for 50% Max.
1.0 V
Start-Up (UVLO) Normal (Duty Cycle Limit) Standby
ENABLE
MODE SELECT
UVLO
SET
R
OSC
C
OSC
OUTPUT
D
MAX
/SS
1.2 V
1.0 V
OFF
ON
Start-Up (UVLO) Normal (Duty Cycle Limit) Standby
Figure 1. Si9145 Timing Diagram (MODE SELECT = High)
Figure 2. Si9145 Timing Diagram (MODE SELECT = Low)
1.0 V
Si9145
Vishay Siliconix
www.vishay.com
8
Document Number: 70021
S-40710—Rev. K, 19-Apr-04
PIN CONFIGURATIONS
13
V
DD
V
S
MODE SELECT OUTPUT
D
MAX
/SS P
GND
COMP UVLO
SET
FB
NI
V
REF
ENABLE
OTS
C
OSC
GND R
OSC
SOIC-16
14
15
16
2
3
4
1
10
11
125
6
7
9
8
Top View
13
V
DD
V
S
MODE SELECT OUTPUT
D
MAX
/SS P
GND
COMP UVLO
SET
FB
NI
V
REF
ENABLE
OTS
C
OSC
GND R
OSC
TSSOP-16
14
15
16
2
3
4
1
10
11
125
6
7
9
8
Top View
ORDERING INFORMATION−SOIC-16
Part Number Temperature Range
Si9145BY-T1
25
_
to 85
_
C
Si9145BY-T1—E3
−25_ to 85_C
ORDERING INFORMATION−TSSOP-16
Part Number Temperature Range
Si9145BQ-T1
25
_
to 85
_
C
Si9145BQ-T1—E3
−25_ to 85_C
PIN DESCRIPTION
Pin 1: V
DD
The positive power supply for all functional blocks except
output driver. A bypass capacitor of 0.1 mF (minimum) is
recommended.
Pin 2: MODE SELECT
This pin is used to enable maximum duty cycle limit and set
output polarity of controller. When connected to V
DD
, the
maximum duty cycle function is controlled by the D
MAX
/SS pin.
The maximum duty cycle limit is usually used for forward,
flyback, and boost converters. The output polarity is high when
the PWM circuitry requires the external device to be turned on.
When connected to GND, the maximum duty cycle is not
limited (usually for buck converters driving a p-channel MOS).
The output polarity is low when the PWM circuitry requires the
external PMOS to be turned on.
Pin 3: D
MAX
/SS
D
MAX
/SS pin controls the maximum duty cycle achievable by
the PWM circuitry when the MODE SELECT = V
DD
.
When D
MAX
/SS is at less than 1.0 V (typical) the OUTPUT is
held low (0% duty cycle). When D
MAX
/SS is at more than 1.5 V
(typical), the PWM circuitry can achieve 100% duty cycle. With
voltage at D
MAX
/SS between 1.0 V and 1.5 V, the maximum
duty cycle is proportionally limited to this voltage.
The addition of external components can implement a soft
start function.
Pin 4: COMP
This pin is the output of the error amplifier. A compensation
network is connected from this pin to the FB pin to stabilize the
system. This pin drives one input of the internal pulse width
modulation comparator.
Pin 5: FB
The inverting input of the error amplifier. External resistors are
connected to this pin to set the regulated output voltage. The
compensation network is also connected to this pin.
Pin 6: NI
The non-inverting input of the error amplifier. In normal
operation it is externally connected to the V
REF
pin.
Pin 7: V
REF
This pin supplies 1.5 V trimmed to "1.5%. The reference
voltage is generated by a band-gap reference.
Pin 8: GND
Negative return for V
DD
.
Si9145
Vishay Siliconix
Document Number: 70021
S-40710—Rev. K, 19-Apr-04
www.vishay.com
9
Pin 9: R
OSC
This pin is the equivalent of a 1.0-V voltage source derived
from the on-chip V
REF
. When a low T.C. resistor is externally
connected from this pin to GND, a temperature independent
current is generated internally. This current is used as the
charging current source connected to the C
OSC
pin. The
current is internally multiplied by 2 and is used as the
discharging current source connected to the C
OSC
pin.
Therefore, the external resistor is one of the factors that
determine the oscillator frequency.
Pin 10: C
OSC
An external capacitor is connected to this pin to set the
oscillator frequency. Internal current sources alternately
charge and discharge the external capacitor. The oscillator
waveform is a symmetrical triangular type with a typical voltage
swing between 1.0 V and 1.5 V.
f
OSC
]
0.7
R
OSC
< C
OSC
Pin 11: OTS
This pin indicates an over-temperature condition on the device
when the output is low. The output is latched low and is reset
with the ENABLE pin going low then high, or by turning power
off and on.
Pin 12: ENABLE
A logic high on this pin allows normal operation. A logic low
places the chip in the standby mode. In standby mode normal
operation is disabled, supply current is reduced, the oscillator
stops and the output is held high for MODE SELECT = low, and
low for MODE SELECT = high.
Pin 13: UVLO
SET
This pin will place the chip in the standby mode if the UVLO
SET
voltage drops below 1.2 V. Once the UVLO
SET
voltage
exceeds 1.2 V, the chip operates normally. There is a built-in
hysteresis of 200 mV.
Pin 14: P
GND
The negative return for the V
S
supply.
Pin 15: OUTPUT
This CMOS push-pull output pin drives the external MOSFET
and is capable of sinking 150 mA or sourcing 130 mA with V
S
equal to 2.7 V.
Pin 16: V
S
The positive terminal of the power supply which powers the
CMOS output driver. A bypass capacitor is required.
P1-P3P4-P6P7-P9P10-P12P13-P14

SI9145BQ-T1-E3

Mfr. #:
Buy SI9145BQ-T1-E3
Manufacturer:
Vishay / Siliconix
Description:
Switching Controllers Lo V-Hi Freq Swmode Controller
Lifecycle:
New from this manufacturer.
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