73S8010C Data Sheet DS_8010C_024
4 Rev. 1.5
Figures
Figure 1: 73S8010C Block Diagram ............................................................................................................. 2
Figure 2: I
2
C Bus Write Protocol ................................................................................................................... 8
Figure 3: I
2
C Bus Read Protocol ................................................................................................................... 9
Figure 4: I
2
C Bus Timing Diagram ................................................................................................................ 9
Figure 5: Power Down Mode Operation ...................................................................................................... 12
Figure 6: Activation Sequence .................................................................................................................... 12
Figure 7: Deactivation Sequence ................................................................................................................ 13
Figure 8: FAULT Functions, INT operation ................................................................................................. 13
Figure 9: Warm Reset operation ................................................................................................................. 14
Figure 10: I/O Timing .................................................................................................................................. 14
Figure 11: 73S8010C – Typical Application Schematic .............................................................................. 15
Figure 12: DC – DC Converter Efficiency (V
CC
= 5 V) ................................................................................ 18
Figure 13: DC – DC Converter Efficiency (V
CC
= 3 V) ................................................................................ 18
Figure 14: 32-pin QFN Package Drawing ................................................................................................... 22
Figure 15: 28-pin SO Package Drawing ..................................................................................................... 23
Tables
Table 1: Device Address Selections ............................................................................................................. 7
Table 2: Host Control Register ...................................................................................................................... 7
Table 3: Host Status Register ....................................................................................................................... 8
Table 4: Choice of Vcc Capacitor ............................................................................................................... 10
