73S8010C Data Sheet DS_8010C_024
14 Rev. 1.5
A power-on-reset (POR) event will reset all of the control and status registers to their default states. A V
DD
fault
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that
creates interval “t
1
,” will not clear the interrupt until V
DD
is valid for at least the t
1
time. The V
DD
fault can be
considered valid for V
DD
as low as 1.5 to 1.8 volts. At the lower range of the V
DD
fault, POR will be asserted.
11 Warm Reset
The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I
2
C Control
register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
Figure 9: Warm Reset operation
12 I/O Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are high when the
activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for more
details on when the I/O reception is enabled.
The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable
bit (bit 7 of the Control register) is set, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected
then both I/O lines return to their neutral state. The delay between the I/O signals is shown in Figure 10.
Figure 10: I/O Timing
Warm Reset
(bit 1)
RST
t
1
t
2
t
3
IO
t
1
> 1.5 µs, Warm Reset Starts
t
2
= 42000 card clock cycles, End of Warm Reset
t
3
= Resets Warm Reset bit 1 when detected ATR or Mute
Delay from I/O to I/OUC: t
IO_HL
= 100 ns t
IO_LH
= 25 ns
Delay from I/OUC to I/O: t
I/OUC_HL
= 100 ns t
I/OUC_LH
= 25 ns
