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IDT71V2558S166PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
6.42
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used
(1)
Write Operation with Clock Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A
1
H L L L X X X Clock Valid
n+3 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+4 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
0
Address A
0
Read out (bus trans.)
n+6 A
3
HL LLXLQ
1
Address A
1
Read out (bus trans.)
n+7 A
4
HL LLXLQ
2
Address A
2
Read out (bus trans.)
4875 tbl 17
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN BW
x
OE
I/O
Comments
nA
0
L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clock n+1 Ignored.
n+2 A
1
L L LLLXXClock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
L L LLLXD
0
Write Data D
0
n+6 A
3
L L LLLXD
1
Write Data D
1
n+7 A
4
L L LLLXD
2
Write Data D
2
4875 tbl 18
6.42
14
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used
(1)
Write Operation with Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
HL LLXLQ
0
Address A
0
Read out. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
1
Address A
1
Read out. Deselected.
n+7 A
2
H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q
2
Address A
2
Read out. Deselected.
4875 tbl 19
Cycle
Address
R/
W
ADV/
LD
CE
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
L L LLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
4875 tbl 20
6.42
IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
(VDDQ = 2.5V)
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(1)
(VDD = 3.3V±5%)
Figure 1. AC Test Load
AC Test Loads
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O
Z
0
=50Ω
4875 drw 04
,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
4875 drw 05
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LI
|
LBO Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Voltage I
OL
= +6mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -6mA, V
DD
= Min. 2.0
___
V
4875 tbl 21
Symbol Parameter Test Conditions
200MHz 166MHz 133MHz 100MHz
Unit
Com'l Only Com'l Ind Com'l Ind Com'l Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
400 350 360 300 310 250 260 mA
I
SB1
CMOS Standby
Power Supply Current
Device Deselected, Outputs
Open, V
DD
= Max., V
IN
> V
HD
or
<
V
LD
, f = 0
(2,3)
40 40 45 40 45 40 45 mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs
Open, V
DD
= Max., V
IN
> V
HD
or
< V
LD
,
f = f
MAX
(2.3)
130 120 130 110 120 100 110 mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN
>
V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40 40 45 40 45 40 45 mA
4875 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 2.5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
4875 tbl 23
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IDT71V2558S166PF

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Description:
IC SRAM 4.5M PARALLEL 100TQFP
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