DS2476Q+U Datasheet DS2476Q+T, DS2476Q+U | P1-P3

General Description

The DS2476 is a secure ECDSA and HMAC SHA-256

coprocessor companion to the DS28C36. The copro-

cessor can compute any required HMACs or ECDSA

signatures to do any operation on the DS28C36. The

DS2476 provides a core set of cryptographic tools derived

from integrated asymmetric (ECC-P256) and symmetric

(SHA-256) security functions. In addition to the security

services provided by the hardware implemented crypto

engines, the device integrates a FIPS/NIST true random

number generator (RNG), 8Kb of secured EEPROM, a

decrement-only counter, two pins of configurable GPIO,

and a unique 64-bit ROM identification number (ROM ID).

The ECC public/private key capabilities operate from

the NIST defined P-256 curve and include FIPS 186

compliant ECDSA signature generation and verification

to support a bidirectional asymmetric key authentication

model. The SHA-256 secret-key capabilities are compli-

ant with FIPS 180 and are flexibly used either in conjunc-

tion with ECDSA operations or independently for multiple

HMAC functions.

Two GPIO pins can be independently operated under

command control and include configurability supporting

authenticated and nonauthenticated operation including

an ECDSA-based crypto-robust mode to support secure-

boot of a host processor. This secure boot method can

also be used to enable the coprocessor functions.

DeepCover embedded security solutions cloak sensitive

data under multiple layers of advanced security to provide

the most secure key storage possible. To protect against

device-level security attacks, invasive and noninvasive

countermeasures are implemented including active die

shield, encrypted storage of keys, and algorithmic methods.

Applications

● IoT Node Crypto-Protection

● Accessory and Peripheral Secure Authentication

● Secure Storage of Cryptographic Keys for a Host

Controller

● Secure Boot or Download of Firmware and/or System

Parameters

Benets and Features

● ECC-256 Compute Engine

• FIPS 186 ECDSA P256 Signature and Verication

• ECDH Key Exchange with Authentication Prevents

Man-in-the-Middle Attacks

• ECDSA Authenticated R/W of Congurable

Memory

● FIPS 180 SHA-256 Compute Engine

• HMAC

● SHA-256 OTP (One-Time Pad) Encrypted R/W of

Configurable Memory Through ECDH Established Key

● Two GPIO Pins with Optional Authentication Control

• Open-Drain, 4mA/0.4V

• Optional SHA-256 or ECDSA Authenticated On/Off

and State Read

• Optional ECDSA Certicate to Set On/Off after

Multiblock Hash for Secure Boot

● RNG with NIST SP 800-90B Compliant Entropy

Source with Function to Read Out

● Optional Chip Generated Pr/Pu Key Pairs for ECC

Operations

● 17-Bit One-Time Settable, Nonvolatile Decrement-

Only Counter with Authenticated Read

● 8Kbits of EEPROM for User Data, Keys, and

Certificates

● Unique and Unalterable Factory Programmed 64-Bit

Identification Number (ROM ID)

• Optional Input Data Component to Crypto and Key

Operations

● I

C Communication, 100kHz and 400kHz

● Operating Range: 3.3V ±10%, -40°C to +85°C

● 6-Pin TDFN Package

Ordering Information appears at end of data sheet.

Typical Application Circuit appears at end of data sheet.

19-8589; Rev 0; 7/16

DS2476 DeepCover Secure Coprocessor

EVALUATION KIT AVAILABLE

ABRIDGED DATA SHEET

Voltage Range on Any Pin Relative to GND ..........-0.5V to 4.0V

Maximum Current into Any Pin...........................................20mA

Operating Temperature Range ........................... -40°C to +85°C

Junction Temperature ...................................................... +150°C

Storage Temperature Range ............................ -55°C to +125°C

Lead temperature (soldering, 10s) ..................................+300°C

Soldering Temperature (reflow) ...................................... +260°C

Electrical Characteristics

= -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

2.97 3.3 3.63 V

Active Supply Current I

(Note 2) 300 µA

Standby Supply Current I

CCS

250 µA

Computation Current I

CMP

Refer to full data sheet mA

GPIO

Output Low PIO V

0.4 V

Input Low PIO V

-0.3

0.3V

Input High PIO V

0.7V

0.3V

Leakage current I

-10 +10 µA

ECC ENGINE

Generate ECDSA Signature Time t

GES

Refer to full data sheet

Generate ECC Key Pair t

GKP

Coprocessor ECDSA Verify Signature

or Compute ECDH Time

VES

SHA-256 ENGINE

Computation Time (HMAC or RNG) t

CMP

Refer to full data sheet ms

EEPROM

W/E Endurance NCY (Notes 4, 5) 100K —

Read Memory Time t

1 ms

Write Memory Time t

15 ms

Data Retention t

= +85°C (Notes 6, 7)

10 years

C SCL AND SDA PINS (Note 8)

Low-Level Input Voltage V

-0.3

0.15 ×

High-Level Input Voltage V

0.7 ×

0.3V

Hysteresis of Schmitt Trigger Inputs V

HYS

(Note 9)

0.05 ×

Low-Level Output Voltage at 4mA Sink

Current

0.4 V

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Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

ABRIDGED DATA SHEET

= -40°C to +85°C.) (Note 1)

Note 1: Limits are 100% production tested at T

= +25°C and/or T

= +85°C. Limits over the operating temperature range and

relevant supply voltage range are guaranteed by design and characterization. Typical values at +25°C

Note 2: Operating current continuously reading memory at 400kHz with < 25ns rise and fall times on SDA and SCL.

Note 3: Refer to full data sheet.

Note 4: Write-cycle endurance is tested in compliance with JESD47H.

Note 5: Not 100% production tested; guaranteed by reliability qualification.

Note 6: Data retention is tested in compliance with JESD47H.

Note 7: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 8: All I

C timing values are referred to V

IH(MIN)

and V

IL(MAX)

levels, except for t

, whichis measured from V

IH(MIN)

to 0.3 x V

Note 9: Guaranteed by design and/or characterization only. Not production tested.

Note 10: System requirement.

Note 11: The DS2476 provides a hold time of at least 100ns for the SDA signal (referred to the V

IH(MIN)

of the SCL signal) to bridge

the undefined region of the falling edge of SCL. The master can provide a hold time of 0ns when writing to the device.

Note 12: The maximum t

HD:DAT

has only to be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal. If the

clock stretches the SCL, the data must be valid by the set-up time before it releases the clock (I

C-bus specification Rev.

03, 19 June 2007).

Note 13: A fast-mode I

C-bus device can be used in a standard-mode I

C-bus system, but the requirement t

SU:DAT

≥ 250ns must

then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device

does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tr max + t

SU:DAT

= 1000 +

250 = 1250ns (according to the standard-mode I

C-bus specification) before the SCL line is released. Also, the acknowl-

edge timing must meet this set-up time. (I

C-bus specification Rev. 03, 19 June 2007)

Note 14: C

= total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending

on the actual operating voltage and frequency of the application (I

C-bus specification Rev. 03, 19 June 2007).

Note 15: I

C communication should not take place for max t

OSCWUP

time following a power-on reset.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Fall Time from V

IH(MIN)

IL(MAX)

with a Bus Capacitance from

10pF to 400pF

(Note 9) 30 ns

Pulse Width of Spikes that are

Suppressed by the Input Filter

(Note 9) 50 ns

Input Current with an Input Voltage

Between 0.1VCCmax and 0.9VCCmax

II -10 +10 µA

Input Capacitance CI (Note 9) 10 pF

SCL Clock Frequency f

SCL

(Note 10) 0 400 kHz

Hold Time (Repeated) START

Condition

HD:STA

After this period, the rst clock

pulse is generated

0.6 µs

LOW Period of the SCL Clock t

LOW

1.3 µs

HIGH Period of the SCL Clock t

HIGH

0.6 µs

Setup Time for a Repeated START

Condition

SU:STA

0.6 µs

Data Hold Time t

HD:DAT

(Notes 9, 11, 12) 0.9 µs

Data Setup Time t

SU:DAT

(Note 13) 100 ns

Setup Time for STOP Condition t

SU:STO

0.6 µs

Bus Free Time Between a STOP and

START Condition

BUF

1.3 µs

Capacitive Load for Each Bus Line C

(Notes 10, 14) 400 pF

Warm-Up Time t

OSCWUP

(Note 15) 250 µs

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Electrical Characteristics (continued)

ABRIDGED DATA SHEET

P1-P3 P4-P6 P7-P8

DS2476Q+U

Mfr. #:

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DS2476Q+U

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