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MC100EP33DTR2G

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 11
1 Publication Order Number:
MC10EP33/D
MC10EP33, MC100EP33
3.3V/5V ECL B4 Divider
Description
The MC10/100EP33 is an integrated B4 divider. The differential
clock inputs.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
Features
• 320 ps Propagation Delay
• Maximum Frequency = > 4 GHz Typical
• PECL Mode Operating Range:
V
CC
= 3.0 V to 5.5 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
EE
• V
BB
Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC−8 NB
D SUFFIX
CASE 751−07
MARKING DIAGRAMS*
TSSOP−8
DT SUFFIX
CASE 948R−02
ALYWG
G
HP64
ALYWG
G
KP64
1
8
1
8
1
8
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D
.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
8
HEP64
ALYW
G
1
8
KEP64
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
SOIC−8 NB TSSOP−8 DFN8
5Q MG
G
14
3L MG
G
14
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5Q = MC10 Y = Year
3L = MC100 W = Work Week
M
= Date Code
G = Pb-Free Package
(Note: Microdot may be in either location)
MC10EP33, MC100EP33
www.onsemi.com
2
1
2
3
45
6
7
8
Q
V
EE
V
CC
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
CLK
Q
CLK
V
BB
RESET
R
B4
Table 1. PIN DESCRIPTION
PIN
CLK*, CLK*
Reset* ECL Asynchronous Reset
FUNCTION
ECL Clock Inputs
Table 2. TRUTH TABLE
CLK
X
Z
CLK
X
Z
RESET
Z
L
Q
L
F
Q
H
F
Z = LOW to HIGH Transition
Z
= HIGH to LOW Transition
F = Divide by 4 Function
V
BB
Reference Voltage Output
Q, Q ECL Data Outputs
V
CC
Positive Supply
V
EE
Negative Supply
* Pins will default LOW when left open.
EP (DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnected,
floating open.
Figure 2. Timing Diagram
CLK
RESET
Q
t
RR
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor NA
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8 NB
TSSOP−8
DFN8
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in
Transistor Count 91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC10EP33, MC100EP33
www.onsemi.com
3
Table 4. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 6 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −6 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6
−6
V
I
out
Output Current Continuous
Surge
50
100
mA
I
BB
V
BB
Sink/Source ±0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
T
sol
Wave Solder < 2 to 3 sec @ 248°C 265 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
T
sol
Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 2) DFN8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL (V
CC
= 3.3 V, V
EE
= 0 V (Note 1))
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 18 26 40 18 26 40 18 26 40 mA
V
OH
Output HIGH Voltage (Note 2) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
V
OL
Output LOW Voltage (Note 2) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
V
IH
Input HIGH Voltage (Single-Ended) 2090 2415 2155 2480 2215 2540 mV
V
IL
Input LOW Voltage (Single-Ended) 1365 1690 1430 1755 1490 1815 mV
V
BB
Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
2.0 3.3 2.0 3.3 2.0 3.3 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to −2.2 V.
2. All loading with 50 W to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
P1-P3P4-P6P7-P9P10-P11

MC100EP33DTR2G

Mfr. #:
Buy MC100EP33DTR2G
Manufacturer:
ON Semiconductor
Description:
Multipliers / Dividers 3.3V/5V ECL Divide By 4 Divider
Lifecycle:
New from this manufacturer.
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