Data Sheet AD8005
Amp 1 has its +input driven with the ac-coupled input signal
while the +input of Amp 2 is connected to a bias level of +2.5 V.
Thus the −input of Amp 2 is driven to virtual +2.5 V by its output.
Therefore, Amp 1 is configured for a noninverting gain of five,
(1 + R
F1
/R
G
), because R
G
is connected to the virtual +2.5 V of
the –input of Amp 2.
When the +input of Amp 1 is driven with a signal, the same
signal appears at the −input of Amp 1. This signal serves as an
input to Amp 2 configured for a gain of −5, (−R
F2
/R
G
). Thus the
two outputs move in opposite directions with the same gain and
create a balanced differential signal.
This circuit can be simplified to create a bipolar in/bipolar out
single-ended to differential converter. Obviously, a single supply
is no longer adequate and the −V
S
pins must now be powered
with −5 V. The +input to Amp 2 is tied to ground. The ac coupling
on the +input of Amp 1 is removed and the signal can be fed
directly into Amp 1.
LAYOUT CONSIDERATIONS
In order to achieve the specified high-speed performance of the
AD8005, the user must be attentive to board layout and component
selection. Proper R
F
design techniques and selection of components
with low parasitics are necessary.
The printed circuit board (PCB) must have a ground plane that
covers all unused portions of the component side of the board.
This provides a low impedance path for signals flowing to ground.
Remove the ground plane from the area under and around the
chip (leave about 2 mm between the pin contacts and the
ground plane). This helps to reduce stray capacitance. If both
signal tracks and the ground plane are on the same side of the
PCB, also leave a 2 mm gap between ground plane and track.
Figure 34. Inverting and Nonconverting Configurations
Chip capacitors have low parasitic resistance and inductance and
are suitable for supply bypassing (see Figure 34). Make sure that
one end of the capacitor is within 1/8 inch of each power pin
with the other end connected to the ground plane. An additional
large (0.47 µF − 10 µF) tantalum electrolytic capacitor must also
be connected in parallel. This capacitor supplies current for fast,
large signal changes at the output. It must not necessarily be as
close to the power pin as the smaller capacitor.
Locate the feedback resistor close to the inverting input pin in
order to keep the stray capacitance at this node to a minimum.
Capacitance variations of less than 1.5 pF at the inverting input
significantly affect high-speed performance.
Use stripline design techniques for long signal traces (that is,
greater than about 1 inch). Striplines must have a characteristic
impedance of either 50 Ω or 75 Ω. For the stripline to be effective,
correct termination at both ends of the line is necessary.
Table 5. Typical Bandwidth vs. Gain Setting Resistors
Gain R
F
R
G
R
T
Small Signal −3 dB BW
(MHz), V
S
= ±5 V
−1 1.49 kΩ 1.49 kΩ 52.3 120 MHz
−10 1 kΩ 100 Ω 100 Ω 60 MHz
+1 2.49 kΩ ∞ 49.9 Ω 270 MHz
+10 499 Ω 56.2 Ω 49.9 Ω 40 MHz
INCREASING FEEDBACK RESISTORS
Unlike conventional voltage feedback op amps, the choice of
feedback resistor has a direct impact on the closed-loop bandwidth
and stability of a current feedback op amp circuit. Reducing the
resistance below the recommended value makes the amplifier
more unstable. Increasing the size of the feedback resistor
reduces the closed-loop bandwidth.
Figure 35. Saving Power by Increasing Feedback Resistor Network
In power-critical applications where some bandwidth can be
sacrificed, increasing the size of the feedback resistor yields
significant power savings. A good example of this is the gain of
+10 case. Operating from a bipolar supply (±5 V), the quiescent
current is 475 µA (excluding the feedback network). The recom-
mended feedback and gain resistors are 499 Ω and 56.2 Ω
respectively. In order to drive an rms output voltage of 2 V, t h e
output must deliver a current of 3.6 mA to the feedback network.
Increasing the size of the resistor network by a factor of 10, as
shown in Figure 35, reduces this current to 360 µA; however,
the closed loop bandwidth decreases to 20 MHz.
C1
0.01µF
C2
0.01µF
C3
10µF
C4
10µF
INVERTING CONFIGURATION
V
IN
R
G
R
T
R
F
R
O
V
OUT
+V
S
–V
S
C1
0.01µF
C2
0.01µF
C3
10µF
C4
10µF
V
IN
R
G
R
T
R
F
R
O
NONINVERTING CONFIGURATION
V
OUT
+V
S
–V
S
12146-034
360µA (rms)
V
OUT
2V (rms)
+5V
4.99kΩ562Ω
–5V
AD8005
V
IN
0.2V (rms)
QUIESCENT CURRENT
475µA (MAX)
12146-035
Rev. B | Page 11 of 16
