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74HCT597N,652

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 13 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9. input (MR) to (Q), output propagation delays and (MR) pulse width
W
:
W
3+/
9
,
*1'
9
2+
9
2/
4RXWSXW
05LQSXW
9
0
9
0
DDD
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 10. Input (PL) to (Q), output propagation delays, PL pulse width and output transition times
I
PD[
W
:
W
3/+
W
3+/
9
,
*1'
9
2+
9
2/
4RXWSXW
3/
LQSXW
9
0
9
0
DDD
W
7+/
W
7/+


Measurement points are given in Table 8.
Fig 11. Input (MR) to shift clock (SHCP) and storage clock (STCP) recovery times
W
UHF
9
,
*1'
9
,
*1'
6+&3
LQSXW
05LQSXW
9
0
9
0
DDD
74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 14 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
Measurement points are given in Table 8.
Fig 12. Hold and set-up times for (DS), (Dn) inputs to (SHCP), (STCP) inputs
DDD
SRVLWLYH
'6'QLQSXW
6+&3
LQSXW
9
0
9
0
9
0
*1'
9
,
*1'
9
,
*1'
9
,
QHJDWLYH
'6'QLQSXW
67&3LQSXW
9
0
*1'
9
,
W
K
W
VX
W
K
W
VX
Measurement points are given in Table 8.
Fig 13. Set-up times for (PL) input to (SHCP) input
DDD
3/LQSXW
6+&3
LQSXW
9
0
9
0
*1'
9
,
*1'
9
,
W
K
W
VX
Table 8. Measurement points
Type Input Output
V
M
V
I
V
M
74HC597 0.5 V
CC
GND to V
CC
0.5 V
CC
74HCT597 1.3 V GND to 3 V 1.3 V
74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 15 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
Test data is given in Table 9.
Definitions test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch.
Fig 14. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 9. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
, t
PHZ
t
PZL
, t
PLZ
74HC597 V
CC
6ns 15pF, 50 pF 1k open GND V
CC
74HCT597 3 V 6 ns 15 pF, 50 pF 1 k open GND V
CC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

74HCT597N,652

Mfr. #:
Buy 74HCT597N,652
Manufacturer:
NXP Semiconductors
Description:
Counter Shift Registers 8-BIT SHIFT REG
Lifecycle:
New from this manufacturer.
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