AD561SD/883B Datasheet AD561JNZ, AD561KNZ, AD561JD | P7-P9

AD561

–6–

REV. A

ratio such that it is unnecessary to use additional area for ladder

resistors. The current in Q

is added to the ladder to balance it

properly, but is not switched to the output; thus, full scale is

1023/1024 3 2 mA.

The switching cell of Q

, Q

and Q

serves to steer the cell

current either to ground (BIT 1 low) or to the DAC output

(BIT 1 high). The entire switching cell carries the same current

whether the bit is on or off, minimizing thermal transients and

ground current errors. The logic threshold, which is generated

from the positive supply (see Digital Logic Interface), is applied

to one side of each cell.

Figure 6. Digital Threshold vs. Positive Supply

DIGITAL LOGIC INTERFACE

All standard positive supply logic families interface easily with

the AD561. The digital code is positive true binary (all bits

high, Logic “1,” gives positive full scale output). The logic input

load factor (100 nA max at Logic “1,” –25 µA max at Logic “0,”

3 pF capacitance), is less than one equivalent digital load for all

logic families, including unbuffered CMOS. The digital

threshold is set internally as a function of the positive supply, as

shown in Figure 6. For most applications, connecting V

to the

positive logic supply will set the threshold at the proper level for

maximum noise immunity. For nonstandard applications, refer

to Figure 6 for threshold levels. Uncommitted bit input lines

will assume a “1” state (similar to TTL), but they are high

impedance and subject to noise pickup. Unused digital inputs

should be directly connected to ground or V

, as desired.

SETTLING TIME

The high speed NPN current steering switching cell and

internally compensated reference amplifier of the AD561 are

specifically designed for fast settling operation. The typical

settling time to ±0.05% (1/2 LSB) for the worst case transition

(major carry, 0111111111 to 1000000000) is less than 250 ns;

the lower order bits all settle in less than 200 ns. (Worst case

settling occurs when all bits are switched, especially the MSB.)

Full realization of this high speed performance requires strict

attention to detail by the user in all areas of application and

testing.

The settling time for the AD561 is specified in terms of the

current output, an inherently high speed DAC operating mode.

However, most DAC applications require a current-to-voltage

conversion at some point in the signal path, although an

unbuffered voltage level (not using an op amp) is suitable for

use in a successive-approximation A/D converter (see page 8),

or in many display applications. This form of conversion can

give very fast operation if proper design and layout is done. The

fastest voltage conversion is achieved by connecting a low value

resistor directly to the output, as shown in Figure 9. In this case,

the settling time is primarily determined by the cell switching

time and by the RC time constant of the AD561 output capaci-

tance of 25 picofarads (plus stray capacitance) combined with the

output resistor value. Settling to 0.05% of full scale (for a full-

scale transition) requires 7.6 time constants. This effect is

important for R > 1 kΩ.

If an op amp must be used to provide a low impedance output

signal, some loss in settling time will be seen due to op amp

dynamics. The normal current-to-voltage converter op amp

circuits are shown in the applications circuits on page 5, using

the fast settling AD509. The circuits shown settle to ±1/2 LSB

in 600 ns unipolar and 1.1 µs bipolar. The DAC output

capacitance, which acts as a stray capacitance at the op amp

inverting input, must be compensated by a feedback capacitor,

as shown. The value should be carefully chosen for each

application and each op amp type.

Figure 5. Circuit Diagram Showing Reference, Control Amplifier, Switching Cell, R-2R Ladder, and Bit Arrangement

of AD561

AD561

–7–

REV. A

Fastest operation will be obtained by minimizing lead lengths,

stray capacitance and impedance levels. Both supplies should be

bypassed near the devices; 0.1 µF will be sufficient since the

AD561 runs at constant supply current regardless of input code.

POWER SUPPLY SELECTION

The AD561 will operate over a wide range of power supply

voltages, with a total supply from 15.3 to 33 volts. Symmetrical

supplies are not required, and in many applications not recom-

mended. Maximum allowable supplies are ±16.5 V.

The positive supply level determines the digital threshold level,

as explained on page 6 and shown in Figure 6. It is therefore

recommended that V

be connected directly to the digital

supply for best threshold match.

Positive output voltage compliance range is unaffected by the

positive supply level because of the open collector output stage

design; thus the full +10 volt compliance is available even with a

+5 volt V

level. Power supply rejection is excellent, so that

digital supply noise will not be reflected to the output. but use

of a 0.1 µF bypass capacitor near the AD561 is recommended

for decoupling.

The nominal negative supply level is –15 volts, with an allow-

able range of –10.8 to –16.5 volts. The negative supply level

affects the negative compliance range, as shown in Figure 7.

OUTPUT VOLTAGE COMPLIANCE

The AD561 has a typical output compliance range from –3 to

+10 volts. The output current is unaffected by changes in the

output terminal voltage over that range. This results from the

use of open collector output switching stages in a cascade

configuration, and gives an output impedance of 40 MΩ.

Positive compliance range is limited only by collector break-

down (and is independent of positive supply level), but the

negative range is limited by the required bias levels and resistor

ladder voltage. Negative compliance varies with negative supply,

as shown in Figure 7. The compliance range is guaranteed to be

–2 to +10 volts with V

= –15 volts.

Figure 7. Typical Negative Compliance Range vs.

Negative Supply

DIRECT UNBUFFERED VOLTAGE OUTPUT

The wide compliance range allows direct current-to-voltage

conversion with just an output resistor. Figure 8 shows a

connection using the gain and bipolar output resistors to give a

±1.66 volt bipolar swing. In this situation, the digital code is

complementary binary. Other combinations of internal and

external output resistors (R

) can be used to scale to alternate

voltage ranges, simply by appropriately scaling the 0 to –2 mA

unipolar output current and using the 2.5 volt reference voltage

for bipolar offset. For example, setting R

= 2.5 kΩ gives a ±1

volt range with a 1 kΩ equivalent output impedance. A 0 to +10

volt output can be obtained by connecting the 5 kΩ gain resistor

to 9.99 volts; again the digital code is complementary binary.

Figure 8. Unbuffered Bipolar Voltage Output

HIGH SPEED 10-BIT A/D CONVERTERS

The fast settling characteristics of the AD561 make it ideal for

high speed successive approximation A/D converters. The

internal reference and trimmed application resistors allow a

10-bit converter system to be constructed with a minimum parts

count. Shown here is a configuration using standard compo-

nents; this system completes a full 10-bit conversion in 5.5 µs

unipolar or 12 µs bipolar. This converter will be accurate to

±1/2 LSB of 10 bits and have a typical gain TC of 10 ppm/°C.

In the unipolar mode, the system range is 0 to 9.99 volts,

with each bit having a value of 9.76 mV. For true conversion

accuracy, an A/D converter should be trimmed so that a given

bit code output results from input levels from 1/2 LSB below to

1/2 LSB above the exact voltage which that code represents.

Therefore, the converter zero point should be trimmed with an

input voltage of +4.9 mV; trim R

until the LSB just begins to

appear in the output code (all other bits “0”). For full scale, use

an input voltage of +9.985 volts (10 volts – 1 LSB – 1/2 LSB);

then trim R

again until the LSB just begins to appear (all other

bits “1”).

The bipolar signal range is –5.0 to +4.99 volts. Bipolar offset

trimming is done by applying a +4.9 mV input signal and

trimming R

for the LSB transition (MSB “1,” all other bits

“0.”) Full scale is set by applying –4.995 volts and trimming R

for the LSB transition (all other bits “0”). In many applications,

the pretrimmed application resistors are sufficiently accurate

that external trimmers will be unnecessary, especially in

situations requiring less than full 10-bit ± 1/2 LSB accuracy.

For fastest operation, the impedance at the comparator sum-

ming node must be minimized, as mentioned in the section on

settling time. However, lowering the impedance will reduce the

voltage signal to the comparator (at an equivalent impedance of

1 kΩ, 1 LSB = 2 mV) to the point that comparator performance

will be sacrificed. A 1 kΩ resistor is the optimum value for this

application for 10-bit accuracy. The chart shown in the figure

gives the speed of the ADC for ±1/2 LSB accuracy (and no

missing codes) for 6-, 8- and 10-bit resolution.

AD561

–8–

REV. A

C394e–1–5/97

PRINTED IN U.S.A.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Pin Ceramic Package

D-16

16-Pin Plastic Package

N-16

Figure 9. Fast Precision Analog to Digital Converter

A much faster converter can be constructed by using higher

performance external components. Each individual high-order

bit settles in less than 250 ns; the low-order bits in less than

200 ns. Because of this, a staged clock, which speeds up for

lower bits will improve the speed. Also, a faster comparator and

Schottky TTL or ECL logic would be necessary. 10-bit convert-

ers in the 3 µs to 5 µs range could be built around the AD561

with these techniques.

DIGITAL 4-TO-20 mA OR 1-TO-5 VOLT CONVERTER

A direct digital 4-to-20 mA or 1-to-5 volt line driver can be built

with the AD561 as shown in Figure 10. The 2.5 volt reference is

divided to provide 1 volt at the op amp noninverting input – thus a

zero input code results in a 1 volt output at the Darlington emitter

OUT

). The 2 k feedback resistance converts the nominal 2 mA

(±20%) full-scale output from the AD561 to 4 volts, for a

total output of 5 volts FS. The voltage at the emitter forces a

proportional current through the 250 Ω (which appears at the

collector as I

OUT

) The AD561 current is added to the 4–20 mA

line; thus 5 volts full scale gives 22 mA in the current loop. For

exactly 20 mA, trim the 1 k pot for 4.5 V FS. (A single op amp

circuit will not produce both 1 to 5 volt and

4-to-20 mA outputs simultaneously.)

Figure 10. Digital 4-to-20 mA or 1-to-5 Volt Line Driver

DIGITALLY PROGRAMMABLE SETPOINT

COMPARATOR

Figure 11 demonstrates a high accuracy systems-oriented

setpoint comparator. The 2.5 volt reference is buffered and

amplified by the AD741K to produce an exact 10.000 volt

reference which could be used as a primary system reference for

several such circuits. The +10 volt compliance of the AD561

then allows it to generate a zero to +10 volt output swing

through the 5 kΩ application resistor without an additional op

amp. The digital code for this system will be complementary

binary (all 1s give 0.00 volts out).

Figure 11. Digitally Programmable Set-Point Comparator

P1-P3 P4-P6 P7-P9

AD561SD/883B

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AD561SD/883B

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