CAT1640, CAT1641
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12
Immediate/Current Address Read
The CAT1640 and CAT1641 address counter contains the
address of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would access
data from address N+1. For all devices, N = E = 4,095. The
counter will wrap around to Zero and continue to clock out
valid data. After the CAT1640 and CAT1641 receives its
slave address information (with the R/W
bit set to one), it
issues an acknowledge, then transmits the 8−bit byte
requested. The master device does not send an acknowledge,
but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1640 and CAT1641 acknowledges, the Master
device sends the START condition and the slave address
again, this time with the R/W
bit set to one. The CAT1640
and CAT1641 then responds with its acknowledge and sends
the 8−bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1640 and CAT1641 sends the
initial 8−bit byte requested, the Master will responds with an
acknowledge which tells the device it requires more data.
The CAT1640 and CAT1641 will continue to output an 8−bit
byte for each acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT1640 and
CAT1641 is sent sequentially with the data from address N
followed by data from address N+1. The READ operation
address counter increments all of the CAT1640 and
CAT1641 address bits so that the entire memory array can
be read during one operation.
Figure 11. Selective Read Timing
* = Don’t Care Bit
A
15
–A
8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A
7
–A
0
BYTE ADDRESS SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
DATA
P
*
*
*
S
T
A
R
T
S
T
O
P
Figure 12. Sequential Read Timing
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+xDATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS