USB 2.0 Hi-Speed 2-Port Hub Controller
Datasheet
DS00001701A-page 44
2014 Microchip Technology Inc.
9.5.2 Reset and Configuration Strap Timing
Figure 9.3 illustrates the RESET_N timing requirements and its relation to the configuration strap
signals. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the
minimum period specified.
Refer to Section 8.3, "Resets," on page 35 for additional information on resets. Refer to Section 6.3,
"Device Configuration Straps," on page 27 for additional information on configuration straps.
9.5.3 USB Timing
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set
forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Specification,
Revision 2.0, available at http://www.usb.org.
9.5.4 SMBus Timing
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as
set forth in the System Management Bus Specification. Please refer to the System Management Bus
Specification, Version 1.0, available at http://smbus.org/specs.
9.5.5 I
2
C Timing
All device I
2
C signals conform to the 100KHz Standard Mode (Sm) voltage, power, and timing
characteristics/specifications as set forth in the I
2
C-Bus Specification. Please refer to the I
2
C-Bus
Specification, available at http://www.nxp.com.
Figure 9.3 RESET_N Configuration Strap Timing
Table 9.5 RESET_N Configuration Strap Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
rstia
RESET_N input assertion time 5 us
t
csh
Configuration strap hold after RESET_N deassertion 1 ms
RESET_N
Configuration
Straps
t
rstia
t
csh
