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USB2532I-1080AENTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
USB 2.0 Hi-Speed 2-Port Hub Controller
Datasheet
DS00001701A-page 34
2014 Microchip Technology Inc.
USB host, or a DCP (Dedicated Charging Port) if not connected to a USB host. If the port is not
configured to support battery charging, the port is considered an SDP (Standard Downstream Port).
All charging ports have electrical characteristics different from standard non-charging ports.
A downstream port will behave as a CDP, DCP, or SDP depending on the port’s configuration and
mode of operation. The port will not switch between a CDP/DCP or SDP at any time after initial power-
up and configuration. A downstream port can be in one of three modes shown in the table below.
8.1.2.2 Downstream Battery Charging Configuration
Configuration of ports to support battery charging is performed via the BC_EN configuration straps,
USB configuration, SMBus configuration, or OTP. The Battery Charging Enable Register provides per
port battery charging configuration. Starting from bit 1, this register enables battery charging for each
down stream port when asserted. Bit 1 represents port 1 and so on. Each port with battery charging
enabled asserts the corresponding PRTPWR register bit.
8.1.2.3 Downstream Over-Current Management
It is the devices responsibility to manage over-current conditions. Over-Current Sense (OCS) is
handled according to the USB specification. For battery charging ports, PRTPWR is driven high
(asserted) after hardware initialization. If an OCS event occurs, the PRTPWR is negated. PRTPWR
will be negated for all ports in a ganged configuration. Only the respective PRTPWR will be negated
in the individual configuration.
If there is an over-current event in DCP mode, the port is turned off for one second and is then re-
enabled. If the OCS event persists, the cycle is repeated for a total or three times. If after three
attempts, the OCS still persists, the cycle is still repeated, but with a retry interval of ten seconds. This
retry persists for indefinitely. The indefinite retry prevents a defective device from permanently disabling
the port.
In CDP or SDP mode, the port power and over-current events are controlled by the USB host. The
OCS event does not have to be registered. When and if the hub is connected to a host, the host will
initialize the hub and enable its port power. If the over current still exists, it will be notified at that point.
Table 8.2 Downstream Port Types
USB ATTACH TYPE DP/DM PROFILE
DCP
(Dedicated Charging Port)
Apple charging mode or
China Mode (Shorted < 200ohm) or
MCHP custom mode
CDP
(Charging Downstream Port)
VDP reflected to VDM
SDP
(Standard Downstream Port)
USB Host or downstream hub port
15Kohm pull-down on DP and DM
USB 2.0 Hi-Speed 2-Port Hub Controller
Datasheet
2014 Microchip Technology Inc. DS00001701A-page 35
8.2 Flex Connect
This feature allows the upstream port to be swapped with downstream physical port 1. Only
downstream port 1 can be swapped physically. Using port remapping, any logical port (number
assignment) can be swapped with the upstream port (non-physical).
Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The
FLEXCONNECT configuration bit switches the port, and EN_FLEX_MODE enables the mode.
8.2.1 Port Control
Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.
If EN_FLEX_MODE is set and FLEXCONNECT is not set:
1. PRTPWR1 enters combined mode, becoming PRTPWR1/OCS1_N
2. OCS1_N becomes a don’t care
3. SUSPEND outputs ‘0’ to keep any upstream power controller off
If EN_FLEX_MODE is set and FLEXCONNECT is
set:
1. The normal upstream VBUS pin becomes a don’t care
2. PRTPWR1 is forced to a ‘1’ in combined mode, keeping the port power on to the application
processor.
3. OCS1 becomes VBUS from the application processor through a GPIO
4. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port
8.3 Resets
The device has the following chip level reset sources:
Power-On Reset (POR)
External Chip Reset (RESET_N)
USB Bus Reset
8.3.1 Power-On Reset (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and
reapplied to the device. A timer within the device will assert the internal reset per the specifications
listed in Section 9.5.1, "Power-On Configuration Strap Valid Timing," on page 43.
8.3.2 External Chip Reset (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within
operating range, per the specifications in Section 9.5.2, "Reset and Configuration Strap Timing," on
page 44. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode
and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
USB 2.0 Hi-Speed 2-Port Hub Controller
Datasheet
DS00001701A-page 36
2014 Microchip Technology Inc.
4. The external crystal oscillator is halted.
5. The PLL is halted.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating
Conditions**," on page 40, prior to (or coincident with) the assertion of RESET_N.
8.3.3 USB Bus Reset
In response to the upstream port signaling a reset to the device, the device performs the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0.
2. Sets configuration to: Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the
reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4 Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per
the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional
latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8.3. For
additional information, refer to the USB 2.0 Link Power Management Addendum.
Note: State change timing is approximate and is measured by change in power consumption.
Note: System clocks are stopped only in suspend mode or when power is removed from the device.
8.5 Remote Wakeup Indicator (SUSP_IND)
The remote wakeup indicator feature uses the SUSP_IND as a side band signal to wake up the host
when in suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration
bit in the hub configuration space register CFG3. The only way to control the bit is by configuration
EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset,
or hardware reset. No dynamic reconfiguring of this capability is possible.
Table 8.3 LPM State Definitions
STATE DESCRIPTION ENTRY/EXIT TIME TO L0
L2 Suspend Entry: ~3 ms
Exit: ~2 ms
L1 Sleep Entry: ~65 us
Exit: ~100 us
L0 Fully Enabled (On) -
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

USB2532I-1080AENTR

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Manufacturer:
Microchip Technology
Description:
USB Interface IC 2-pt USB2.0 Hub Cntl Industrial Temp
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