6
LTC1428-50
SERIAL I/O OPERATI G SEQUE CE
U U
Figure 1. 3-Wire Interface Timing Specification
APPLICATIONS INFORMATION
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8-BIT CURRENT OUTPUT DAC
The LTC1428-50 is an 8-bit, current sink output digital-to-
analog (DAC) converter. The LTC1428-50 is guaranteed
monotonic and is digitally adjustable in 256 equal steps.
Upon power up, the counter resets to 1000000B and the
DAC output assumes midrange. The I
OUT
pin can be biased
from 2V to 10V. The LTC1428-50 features a full-scale
output current of 50µA ±3% at room temperature (±5%
over temperature). This device also includes a flexible
serial digital interface that allows easy interconnection to
a variety of digital systems.
DIGITAL INTERFACE
Automatic Mode Selection
The LTC1428-50 includes a serial interface capable of com-
municating with the host system using one of three pro-
tocols; standard 3-wire mode, a 2-wire up/down pulse mode
and a 1-wire increment-only pulse mode. The LTC1428-50
is designed to autoconfigure itself depending on the method
of data presentation. A diagram illustrating this
autodetection behavior is shown in Figure 2. At power-up,
the interface is set to 1-wire pulse mode. If the CS line ever
goes low (as it will at the beginning of a valid 3-wire serial
transfer) the chip immediately reconfigures itself into 3-wire
mode and remains in this mode until power is cycled. If CS
stays high, the device stays in pulse mode and monitors the
UP/DN pin to determine whether to switch to 2-wire mode.
If UP/DN ever goes low (as it will the first time a “down”
command is given) the chip switches into 2-wire pulse
mode and remains in this mode until power is cycled. In a
properly configured 1-wire system, CS and UP/DN will
always remain high. 2-wire pulse mode systems must
provide a single logic low pulse before the first data pulses
are sent to prevent the LTC1428-50 from remaining in
1-wire mode if the first several pulses are logic high.
Standard 3-Wire Mode (Figure 3)
Refer to the Serial Interface Operating Sequence in Figure
1. When operating in 3-wire mode, the LTC1428-50 will
interface directly with most standard 3- or 4-wire serial
interface systems. The clock (CLK) input synchronizes the
data transfer with each input bit captured at the rising edge
of CLK and each output data bit shifted through D
OUT
at the
falling edge. Data is shifted into and out of the LTC1428-
50 starting with the MSB bit. A falling edge at CS initiates
the data transfer and brings the D
OUT
pin out of three-state.
The serial 8-bit data representing the new DAC setting is
shifted into the D
IN
pin. Simultaneously, the previous DAC
setting is shifted out of the D
OUT
pin. After the new data is
D
IN
CLK
CS
D7
D6 D5 D4 D3 D2 D1 D0
Hi-Z
D7′ D6′ D5′ D4′ D3′
D2′
D1′
D0′
D7
t
DZ
Hi-Z
1428-50 F01
D
OUT
t
DO
t
CKHI
t
DH
t
DS
t
CSS
t
CKS
t
CSLO
t
DV
t
CKLO
t
CSH
t
CSHI
t
CKH
Figure 2. LTC1428-50 Operating Modes
POWER-UP
3-WIRE MODE PULSE MODE
1428-50 F02
INCREMENT/
DECREMENT
INCREMENT-
ONLY
CS STAYS
HIGH
CS GOES
LOW
D
IN
(UP/DN)
GOES LOW
D
IN
STAYS
HIGH
