Philips Semiconductors Product data sheet
SC28C94Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
18
SR – Channel Status Register
SR[7] – Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxDA line returns to the marking state
for at least one-half bit time two successive edges of the internal or
external 1X clock. This will usually require a high time of one X1
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.
When this bit is set, the change in break bit in the ISR (ISR[6 or 2])
is set. ISR[6 or 2] is also set when the end of the break condition, as
defined above, is detected. The break detect circuitry is capable of
detecting breaks that originate in the middle of a received character.
However, if a break begins in the middle of a character, it must last
until the end of the next character in order for it to be detected.
SR[6] – Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SR[5]– Parity Error (PE)
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In ‘wake-up mode’, the parity error bit
stores the received A/D (Address/Data) bit.
In the wake-up mode this bit follows the polarity of the A/D parity bit
as it is received. A parity of 1 would normally mean address and
therefore, the end of a data block.
SR[4] – Overrun Error (OE)
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a reset error status command.
SRA[3] – Channel A Transmitter Empty (TxEMTA)
This bit will be set when the transmitter underruns, i.e., both the
TxEMT and TxRDY bits are set. This bit and TxRDY are set when
the transmitter is first enabled and at any time it is re-enabled after
either (a) reset, or (b) the transmitter has assumed the disabled
state. It is always set after transmission of the last stop bit of a
character if no character is in the THR awaiting transmission.
It is reset when the THR is loaded by the CPU, a pending
transmitter disable is executed, the transmitter is reset, or the
transmitter is disabled while in the underrun condition.
SR[2] – Transmitter Ready (TxRDY)
This bit, when set, indicates that the TxFIFO has at least one empty
location that may be loaded by the CPU. It sets when the transmitter
is first enabled. It is cleared when the TxFIFO is full (eight bytes);
the transmitter is reset; a pending transmitter disable is executed;
the transmitter is disabled when it is in the underrun condition. When
this bit is not set characters written to the TxFIFO will not be loaded
or transmitted; they are lost.
SR[1] – RxFIFO Full (FFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all eight FIFO positions are occupied. It is reset
when the CPU reads the FIFO and there is no character in the
receive shift register. If a character is waiting in the receive shift
register because the FIFO is full, FFULL is not reset after reading
the FIFO once.
SR[0] – RxFIFO Ready (RxRDY)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and reset
when the CPU reads the RxFIFO, and no more characters are in the
FIFO.
ACR – Auxiliary Control Register
ACR[7] – Baud Rate Generator Set Select
This bit selects between two sets of baud rates that are available
within each baud rate group generated by the BRG. See Table 6.
Set 1: 50, 110, 134.5, 200, 300, 600, 1.05k, 1.2k, 2.4k, 4.8k, 7.2k,
9.6k, and 38.4k baud.
Set 2: 75, 110, 150, 300, 600, 1.2k, 1.8k, 2.0k, 2.4k, 4.8k, 9.6k,
19.2k, and 38.4k baud.
The selected set of rates is available for use by the receiver and
transmitter.
ACR[6:4] – Counter/Timer Mode and Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source (see Table 7).
The I/O pins available for counter/timer clock source is I/O1a and
I/O1c. The counter/timer clock selection is connected to the I/O1 pin
and will accept the signal on this pin regardless of how it is
programmed by the I/OPCR.
Table 7. ACR[6:4] C/T Clock and Mode Select
[6:4] Mode Clock Source
0 0 0 Counter I/O1 pin
0 0 1 Counter TxCA – 1X clock of Channel A transmitter
0 1 0 Counter TxCB – 1X clock of Channel B transmitter
0 1 1 Counter Crystal or X1/CLK clock divided by 16
1 0 0 Timer I/O1 pin
1 0 1 Timer I/O1 pin divided by 16
1 1 0 Timer Crystal or external clock (X1/CLK)
1 1 1 Timer Crystal or X1/CLK clock divided by 16
The timer mode generates a squarewave
ACR[3:0] – I/O1b, I/O0b, I/O1a, I/O0a Change-of-State Interrupt
Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register, ISR[7], to
be set and thus allow the Change of State Detectors to enter the
bidding process. If a bit is in the ‘on’ state, the setting of the
corresponding bit in the IPCR will also result in the setting of ISR[7],
which may result in the generation of an interrupt output if IMR[7] =
1. If a bit is in the ‘off’ state, the setting of that bit in the IPCR has no
effect on ISR[7].
